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Bits 2-5 A-clock Latches: Latches A and B verify
proper clock sequencing and outputs. Latches C and
D are used with delay lines to generate the clock
timings.
If
improper operation exists. latches A
and B stop the sequence.
A and B Latches
A Clock
A latch
B latch
Clock State
0
0
Clock AO _p_ulse has not occurred.
1
0
Clock AO occurred. Clock Al did not occur.
1
l
Clock AO and Al occurred. Clock step did
not occur. OTC maybe active.
0
l
Clock sti:e_ is active
C and D Latches
A Clock
C latch
r.
latch
Clock State
l
0
Clock AO time
0
l
Clock ste_p_ time
l
1
Clock step time and request was made to
start another si:g_uence.
0
0
Clock Al time or OTC is active or clock
sequence is complete.
Bits 6-7 SP Latches:
1.
Dl
active and:
a.
Rd
rdy or wr rdy are not active. Tic op
has been detected, second op was not yet
examined.
b.
Rd
rdy or wr rdy is active. PCI interrupt
in progress due
to
the PCI flag.
2.
D2 active and:
a. Instruction scan latch is not active. Chan-
nel is performing compare routine for test
I/O.
b. Instruction scan latch is active. Channel
is in idle mode.
Bit 8 Instruction Scan Latch: Channel is either:
1. Idle - clock is cycling.
2. Polling - poll latch is active.
3. Performing unit selection and has not yet
replied to an initial instruction.
Bit 9 Channel in Use: Channel is in operation as a
result of a start, halt or test I/O instruction.
Bit
10
Poll: The channel is attempting to accept
interrupt status from an I/O device.
Pos 4
Pos 5 Pos 5
Bit 3
Bit 10
Bit
tl
Unit
Poll
Poll
Sel in
LA
Int
State Description
Position
End
Reg
LA
0
1
0
Channel has not stacked poll status.
0
1
l
Channel has stacked status; PCl request
is active, common channel has not
honored request.
l
1
I
PCl enable received; channel attempts to
select unit; unit sel, step 1, CL step not
reached.
l
0
l
SEL out sent to unit; polling status taken;
channel has not requested the interrupt
routine.
0
0
1
Channel should have the interrupt routine
in the position register.
Bit
11
Poll Interrupt End: The CPU has received the
polling status, causing channel to reply to status in
with command out.
Bit 12 Instruction Inhibit: This bit gates the instruc-
tion lines when performing a unit selection as the
result of control word chaining.
It
should be reset
before a read store or write fetch operation is
performed.
Bit 13 BC ready: The new byte count information is
available in the selector channel; the interface has
not reached a state permitting modification of the
byte counter. The fourth clock sequence in CCW2
will not occur until BC rdy is inactive.
Bit 14 UA to Bus Out: In unit selection, the unit
address is being gated to bus out. C register byte
O
contains the UA.
Bit 15 Unit Select Adr Out: In unit selection, ad-
dress out is being generated.
Bit 16 Compare equal: In unit selection, the unit
address sent by the channel was the same as that
returned by the 1/0 control unit.
Bit 17 Compare unequal: In unit selection, the unit
address sent by the channel was different from that
returned by the I/O control unit but each has correct
parity.
Appendix B--System Contl'Ol Panel
(3/71)
147
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