Table of Contents
Advertisement
Address card plugging
127
Address compare (IAR)
152
Adjustments, electrical -- see timings/test points
Adjustments, ROS bit plane
100
ALO page key
12
Binary triggers
33
Bump storage, display and store
151
Bump storage addressing
82
Bump storage diagnostics
75
Bump storage exercise
82
Bump storage, scope bump word
41
Cabling
139
CAS logic diagram page key
14
Channel -- see CPU and channels
Channel control section
142
address and data key assignments
143
Check control operation
153
Circuit breakers
123, 12 7
Clear storage
156
Clock advance counter -- see sequence counter
Clocks (gating/controls)
36
free running
39
non-free running
39
selector channel clock control
71
selector channel clock stepping
109
stop triggers
36
2050 clock
80
Common channel -- see CPU and channel&
Contractors/relays
127
Controls
152
152
152
address compare (IAR)
address compare (ROS)
address compare (SAR)
address keys
143, 150
channel maintenance
check control select
142
153
check reset
151
data keys
143, 150
DC off
140
disable interval timer
152
display
151
emergency off
142
enter
143
FLT control select
153
FLT mode
153
force indicators
152
halt loop operations
159
interrupt
153
invert SAR bit 16
142
lamp test
152
load
154
load unit select
154
log out
151
142
manual operation
142
marginal voltage control
marginal voltage select
monitor voltage select
operator section
154
power off
154
140
142
power on
154
22
PSW restart
151
rate select
150
repeat instruction (IAR)
152
repeat instruction (ROS)
152
reset, system
151, 157
reverse data parity
150
roller select
140
selector channel display
143
set IC
151, 156
start
151, 158
stop
151, 158
stop on check
142
storage select
150, 155
storage test select
142
store
151, 155
write
142
Converter-inverter -- see power system
Counters -- see functional units
CPU and channels
CPU parity checking
76
di agnostics
76
multiplexor channel parity checl<ing
77
preventive maintenance schedule
79
selector channel analysis chart
104
selector channel parity checking
77
selector channel timings
103
service checks
80
singleshot timings
109
waveform measurements
80
2050 clock
80
CPU control modes
18
changing status (modes)
36
entries/objectives/controls
19
main store mode
20
ROS mode
20
sequence counter mode
18
Current requirements
139
Cycle tests -- see fault locating tests
Data flow
10
Dead entries -- see SCOPEX
61
Deferred maintenance
11
Diagnose addresses, 1410/7010
115
Diagnose control word -- see linkage control word
40
Diagnose instruction
40
start 1/0
115
Diagnostic mode codes
13
Diagnostic programs
74
Diagnostic teclmiques
11
Dimensions
139
Disk conversion, 1410/7010
114
Disk storage maps, 2302/2314
114
Display
151
ECAD
1
s
12
Emergency Off
142
Emulator diagnostics
Emulator service aids
76
114
Error cheok analysis diagrams
Error checking
76
Error register
77
Error reset
156
Error stops
12
12
Index
(3/71)
INDEX
189
Advertisement
Table of Contents
