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for the FLT load operation and for the first portion
of a logout operation.
Main Store Mode
When the main store mode trigger (KT151) is on,
the system is under control of words read out of
main storage. Main store mode operation provides
continued main storage read-outs from addresses
specified by the instruction address register (IAR).
The IAR is usually incremented by four immediately
before each address is requested. Data read out of
main storage go into the storage data register (SDR).
Main Store Mode Timing
Main store mode timing consists of four half-micro-
second periods (W2, Rl, R2, Wl). In the first
period (W2), a new address is gated into SAR from
the instruction address register (IAR), and a main
storage cycle is initiated. Instructions requiring
gating action to be performed, and which were read
out in the previous main storage cycle, are also
executed at this time.
In the second period (Rl), the SDR is reset.
During the third half-microsecond period (R2),
main storage completes the read portion of its cycle
and a word is read into the SDR.
At the beginning of the fourth half-microsecond
period (Wl), the four SDR parity bits, which con-
stitute the new microorder, are gated into the FLT
op reg.
If
the decoded operation calls for the gating
of the SDR into read only address register (ROAR),
this is performed toward the end of the period.
0 A
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Main
Storage
Op8
(Reset)
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CPU Control
Modes
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During the next first half-microsecond period
(W2), a new ROS cycle is taken if an address has
just been gated into ROAR; otherwise this is a dead
cycle.
Main Store Mode Instructions and Data Paths
With the CPU in MS mode and the storage test switch
in the process position, the four parity-bit positions
of SDR are gated into the FLT op register.
There
are 16 instructions (including no-ops) that may be
decoded in the FLT op reg.
Figure 8 shows the
instructions and data paths available in main store
mode.
Main Store Mode Ripple
If
the storage test switch is not in the process posi-
tion, the data written into storage are controlled by
a set of patterns forced into SDR and selected by
means of positions on the storage test switch.
The available patterns are all zeros, ones,
worst, and reverse worst.
The worst and reverse
worst patterns consist of two words of all zeros and
then two words of all ones or vice versa. The switch-
ing from ones to zeros to ones is controlled by IAR
bits 17 and 28 which are exclusive OR'ed.
ROS Mode
When the ROS mode trigger (KT151) is on, the sys-
tem is under control of read-only storage (ROS).
The system is always in ROS mode during normal
System/360 operations, and may or may not be in
ROS mode during maintenance operations.
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55
56 87
88
97
T
Op 8
(Re•et\
NOTE:
Op
codes 0, 9, and Dore no ops.
FIGURE 8. MS MODE INSTRUCTIONS AND DATA PATHS
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