IBM System/360 2050 Maintenance Manual page 78

Timing Considerations
With the exception of the carry, mover output, and
full-sum checks, all CPU failures cause the machine
status to be frozen the cycle in which the error is
detected. This is done by stopping the clock in time
to prevent the set register pulse of the next cycle,
thereby blocking the register ingating and preserv-
ing the contents of all registers.
The carry, mover output, and full-sum checks,
however, are detected too late in the CPU cycle to
block the next set register pulse. As a result, the
clock is stopped one cycle later than the cycle in
which the error is detected. In this case, the ad-
dress of the microinstruction that was controlling
the machine during the actual error cycle (previous
ROS address) is available in a ROS address backup
register. With this address available it is possible
to "backup" to the previous cycle for error anaiysis.
Check Register
Each parity check circuit sets a unique bit in the
check register. The table below shows the bit
assignment for each position of the check register.
Bit
O
Halt-tsum
u-·1
Bit 1 Half-Sum 8-15
Bit 2 Half-Sum 16-23
Bit
3
Bit 4
Bit 5
Bit
6
Bit
7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit
17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit ::3
Bit 24
Bit 25
Bit 26
Bit 27-31
Half-Sum 24-31
Sum
0-7
Sum 8-15
Sum 16-23
Sum 24-31
Carry
L Byte Counter
M Byte Counter
MD Counter
Length Counter
(Gl)
Length Counter
(G2)
Mover Left Input
Mover Right Input
Mover Output
Unused
Storage Address Register 8-15
Storage Address Register 16-23
Storage Address Register 24-31
ROS
1-30
ROS 32-55
ROS 57-89
Storage Protect
Reserved for LCS Summary Check
Log Request
Reserved for Expansion
Bit 26 is turned on by the logout key or by the
channel requesting an error logout. It may not
represent an actual CPU error.
The error register is displayed on the system
control panel and is included in the logout informa-
tion. It can be reset by the check reset or system
reset pushbuttons or by the diagnose instruction.
It is automatically reset at the conclusion of an error
logout immediately prior to the machine check
interrupt.
Multiplexor and Selector Channel Parity Checking
The multiplexor and selector channel data flow and
addressing are parity checked on the following data
paths and registers:
Control Checks
Byte Counter Parity
Address Out Parity
Operation Parity
Routine Response
Routine Positional
End Control Validity
Interface Checks
Multiple Tags
Address In Parity
Address Compare
Status Parity
Time-out
In addition, the following CPU failure detection
circuits are active: SAR, mover, adder, and ROS.
Data entering or leaving the interface is parity
checked as is all data transferred between the chan-
nel and CPU (adder full-sum check). Detected data
errors are not propagated into storage on read op-
erations; data is cycled through the adder to correct
the parity before it is stored (disable mode), or an
error logout and machine check interrupt occur
(process mode).
I/O Errors
I/O errors are handled by IOCS. No I/O error
indicators are displayed on the maintenance console.
Main Storage Parity Checking
All main storage checking is performed in CPU.
The adder output latches provide parity checking for
all transfers to and from storage, because they are
located in the data path between the storage data
register (SDR) and the CPU working registers. The
storage address register (SAR) is also parity
checked.
The following data error handling rules apply
during Model 50 storage operations:
1. On a fetch operation, data set into SDR and
regenerated without being transferred into CPU is
not checked. Checking occurs only when the word
is transferred through the adder output latches into
one of the CPU working registers. An error de-
tected in this word sets the error register whether
it is in an addressed byte or not.
2. During a store operation, data from CPU is
checked on a full word basis even though only a
portion of the word may be set into SDR. An error
detected in this word sets the error register
Maintenance Features (3/71)
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