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Thermal,
CB Trip,
Overvoltoge or
Undervoltoge
I
I
DC OFF
System OFF
Drops K5 through
K 11
(Acl->pter Power )
L----+------'
Break
Time Delay Hold
KI
drops
K34 drops on first voltage and-drops K2
K33 drops
when lost spec down
K34 drops K39
K33 drops K4
Drops K31, K32, K35
lights DC OFF Indicator
FIGURE 113. POWER/DC OFF SEQUENCE
Test
/t) Poin~
4
?
P /N
374982
Acros<>
te5
t
poi nb 2 and 4
(Tes" SCR I and SCR 2)
6
use'
Across tesf points I and 3
(Tests SCR 3 and SCR 4)
FIGURE 114. CONVERTER-INVERTER TESTPOINTS AND WAVEFORMS
SCR Gate Signals
Always check the SCR gate signals when a failure
occurs. The gate signals are the most critical
operating requirement of the inverter. Any abnor-
mal variation from the general voltage wave shapes
shown in Figure 114 will cause the inverter to fail.
The SCR gate signals are measured when the three-
phase input power is off. The large allowable per-
centage variations on the gate signal voltages are
mainly attributable to the correspondingly large
variations of SCR gate impedance. If all of the
timing measurements are out of the specified toler-
ances, a potentiometer located on the oscillator
card may be adjusted to give the correct 2. 5-kc
operating frequency.
If the SCR gate signals are normal, critical
components may be checked at the converter-inverter
terminal boards (Figures 115 and 116) with an ohm-
meter. Hemember that a good rectifier has a high
resistance in only one direction but a good SCR has
a high resistance in both directions.
L.
40
use< •
I 0
usec
L----!-160usec:
i
ICusec:
Notes:
t--- 60
usec
i - -
I, r;:iwe1 should be off before removing JS.
2.
A111plitude of waveforms not c:ritic:al.
3. Use
~cope
inputs added algebraically
Nitl,
S probe inverted,
-15
usec
14
usec
-3usec
I
~
u
-
..
--1
-·
~
+5.9v
++·t+H+
t+++ j+H+j
++
rr
T
...........,
g·
L
200
usec
--1---
200
usec
___.j
Commutate Gate Pulse Unloodect
-5.5V
Power System Service Checks
(3/71)
121
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