Pcie Interface - Quectel SG560D Series Hardware Design

4.16. PCIe Interface

The module provides one PCIe interface, which supports 2-lane PCIe Gen 3 with data rate up to 8 Gbps.
Table 33: Pin Definition of PCIe Interface
Pin Name
PCIE1_REFCLK_P
PCIE1_REFCLK_M
PCIE1_RX0_P
PCIE1_RX0_M
PCIE1_RX1_P
PCIE1_RX1_M
PCIE1_TX0_P
PCIE1_TX0_M
PCIE1_TX1_P
PCIE1_TX1_M
PCIE1_RST_N
PCIE1_CLKREQ_N
PCIE1_WAKE_N
Table 34: Trace Length of Differential Pairs Inside the Module
Pin No. Signal
594 PCIE1_REFCLK_P
593 PCIE1_REFCLK_M
601 PCIE1_TX0_P
600 PCIE1_TX0_M
SG560D_Series_Hardware_Design
Pin No. I/O
594 AIO
593 AIO
597 AI
596 AI
599 AI
598 AI
601 AO
600 AO
603 AO
602 AO
605 DO
606 DI
607 DI
Description
PCIe1 reference clock (+)
PCIe1 reference clock (-)
PCIe1 recive 0 (+)
PCIe1 recive 0 (-)
PCIe1 recive 1 (+)
PCIe1 recive 1 (-)
PCIe1 transmit 0 (+)
PCIe1 transmit 0 (-)
PCIe1 transmit 1 (+)
PCIe1 transmit 1 (-)
PCIe1 reset
PCIe1 clock request
PCIe1 wake up
Length (mm)
19.72
19.65
28.37
28.39
Smart Module Series
Comment
Requires
differential
impedance of
85 Ω.
1.8 V power
domain.
Length Difference (P - M)
0.07
-0.02
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