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Quectel SG865W Series Hardware Design

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SG865W Series
Hardware Design
Smart Module Series
Version: 1.0
Date: 2022-05-20
Status: Released

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Summary of Contents for Quectel SG865W Series

  • Page 1 SG865W Series Hardware Design Smart Module Series Version: 1.0 Date: 2022-05-20 Status: Released...
  • Page 2 Smart Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai...
  • Page 3 Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects.

  • Page 4: Safety Information

    Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 5: About The Document

    Smart Module Series About the Document Revision History Version Date Author Description Glenn GE/ 2022-04-30 Creation of the document Joshua PAN Glenn GE/ 2022-05-20 First official release Joshua PAN SG865W_Series_Hardware_Design 4 / 117...

  • Page 6: Table Of Contents

    Smart Module Series Contents Safety Information ............................3 About the Document ........................... 4 Contents ............................... 5 Table Index ..............................7 Figure Index ..............................9 Introduction ............................11 1.1. Special Marks .......................... 15 Product Overview ..........................16 2.1. Frequency Bands and Functions .................... 17 2.2.
  • Page 7 Smart Module Series 4.12. LCM Interfaces ........................71 4.13. Touch Panel Interfaces ......................74 4.14. Camera Interfaces ........................75 4.14.1. Design Considerations ....................81 4.14.2. Flashlight Interfaces ....................... 86 4.15. Sensor Interfaces ........................86 4.16. Audio Interfaces ........................87 4.17. I2S Interfaces ..........................
  • Page 8 Smart Module Series Table Index Table 1: Special Marks ..........................15 Table 2: Brief Introduction of the Module ....................16 Table 3: Wireless Network Type of the Module ..................17 Table 4: Key Features ..........................17 Table 5: I/O Parameters Definition ......................22 Table 6: Pin Description ..........................
  • Page 9 Smart Module Series Table 42: Bluetooth Transmitting and Receiving Performance ..............96 Table 43: Antenna Design Requirements ....................98 Table 44: Absolute Maximum Ratings ...................... 101 Table 45: The Module’s Power Supply Ratings ..................101 Table 46: SG865W-WF Power Consumption ..................102 Table 47: SG865W-AP Power Consumption ...................
  • Page 10 Smart Module Series Figure Index Figure 1: Functional Diagram ........................20 Figure 2: Pin Assignment (Top View) ......................21 Figure 3: Reference Design for Battery Charging Circuit ................44 Figure 4: Reference Circuit of Power Supply ..................... 45 Figure 5: Voltage Drop Sample ........................46 Figure 6: Structure of Power Supply ......................
  • Page 11 Smart Module Series Figure 42: Plastic Reel Dimension Drawing ..................111 Figure 43: Packaging Process ......................... 112 SG865W_Series_Hardware_Design 10 / 117...

  • Page 12: Introduction

    Smart Module Series Introduction This document defines SG865W series module and describes its air interfaces and hardware interfaces which are connected with your applications. It can help you quickly understand interface specifications, electrical and mechanical details as well as other related information of the module. Associated with application notes and user guides, you can use this module to design and to set up mobile applications easily.
  • Page 13 Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel Wireless Solutions Co., Ltd that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application.
  • Page 14 Smart Module Series Le présent appareil est conforme aux CNR d’ ISED applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux conditions suivantes : (1) le dispositif ne doit pas produire de brouillage pré judiciable, et (2) ce dispositif doit accepter tout brouillage reç u, y compris un brouillage susceptible de provoquer un fonctionnement indé...
  • Page 15 Smart Module Series l'inté grateur OEM sera chargé de ré é valuer le produit final (y compris l'é metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users.

  • Page 16: Special Marks

    Smart Module Series d’inclinaison nécessaires pour rester conforme à l’exigence de la p.i.r.e. applicable au masque d’élévation, énoncé e à la section 6.2.2.3, doivent être clairement indiqués. 1.1. Special Marks Table 1: Special Marks Mark Definition Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported;...

  • Page 17: Product Overview

    Smart Module Series Product Overview SG865W series is a series of smart modules based on Android operating system, and provides industrial grade performance. Its general features are listed below: ⚫ Supports built-in high performance Kryo 585 CPU, Adreno 650 GPU, Adreno 995 DPU, Adreno...

  • Page 18: Frequency Bands And Functions

    Smart Module Series 2.1. Frequency Bands and Functions Table 3: Wireless Network Type of the Module Mode Frequency Bands 2402–2482 MHz Wi-Fi 802.11a/b/g/n/ac/ax 5170–5835 MHz BLE 5.1 (BR/EDR + BLE) 2402–2480 MHz 2.2. Key Features Table 4: Key Features Features Details ⚫...
  • Page 19 Smart Module Series ⚫ Digital MIC ⚫ Audio Interfaces ⚫ MI2S ⚫ TDM/PCM ⚫ 5 × SPI interfaces, only supports master mode SPI Interfaces ⚫ 1.8 V operating voltage with clock rates up to 50 MHz ⚫ Supports up to 9 × I2C interfaces 4 ×...

  • Page 20: Functional Diagram

    Smart Module Series Two-wire UART interface Used for debugging by default Baud rate: 115200 bps by default Bluetooth Features ⚫ BLE 5.1 (SG865W-WF only) ⚫ ANT1 ⚫ ANT2 Antenna Interfaces ⚫ ANT_BT* 50 Ω impedance ⚫ 2.4 GHz and 5 GHz ⚫...
  • Page 21 Smart Module Series -- LCM interfaces -- Touch panel interfaces -- Camera interfaces -- Sensor interfaces -- Audio interfaces -- I2S interfaces -- SPI interfaces -- Emergency Download interface Figure 1: Functional Diagram SG865W_Series_Hardware_Design 20 / 117...

  • Page 22: Pin Assignment

    Smart Module Series 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. PCIE2_ LCD_BL_A TX0_P PCIE2_ PM_PWM1 TX0_M PCIE2_ PCIE2_ FLASH_LED1 LCD_BL_K4 RX0_P TX1_P PCIE2_ PM_PWM2 RX0_M PCIE2_ PCIE2_ LCD_BL_K3 REFCLK_P RX1_P PCIE2_ PCIE2_ FASH_LED3 CABC1 REFCLK_M TX1_M FLASH_LDE2...

  • Page 23: Pin Description

    Smart Module Series 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Power Input/Output Table 6: Pin Description Power Supply...
  • Page 24 Smart Module Series Add a 4.7 μF bypass capacitor if used. If unused, keep this pin open. Power supply for the pull-up of the forced shutdown pin of Vnom = 1.8 V SMB1390 battery charger. LDO12A_1V8 1.8 V output Add a 1.0–4.7 μF bypass max = 300 mA capacitor if used.
  • Page 25 Smart Module Series Power supply for external 1.8 V output of buck Vnom = 1.8 V GPIO’s pull up circuits and level VREG_S4A_1V8 481, 486 max = 500 mA shifting circuit. 471, 476, Power supply for Vnom = VBAT VPH_PWR 477, 482 peripherals max = 2000 mA...
  • Page 26 Smart Module Series RGB Interfaces Pin Name Pin No. Description DC Characteristics Comment Current source for R_LED red LED Current source for G_LED green LED Current source for B_LED blue LED USB Interfaces Pin Name Pin No. Description DC Characteristics Comment Charging power input;...
  • Page 27 Smart Module Series USB0 3.1 channel 1 USB0_SS1_TX_M SuperSpeed transmit USB_CC1 USB Type-C detect 1 USB_CC2 USB Type-C detect 2 USB1 2.0 differential USB1_DP 90 Ω differential impedance. data (+) USB 2.0 standard compliant. USB1 2.0 differential USB1_DM data (-) USB1 3.1 USB1_SS_TX_P SuperSpeed transmit...
  • Page 28 Smart Module Series WCD SoundWire WCD_SWR_TX_CLK 92 transmit clock WCD_SWR_TX_DAT WCD SoundWire transmit data 0 WCD_SWR_TX_DAT WCD SoundWire transmit data 1 WCD SoundWire WCD_SWR_RX_CLK 82 receive clock WCD_SWR_RX_DAT WCD SoundWire receive data 0 WCD_SWR_RX_DAT WCD SoundWire receive data 1 LPI digital MIC3 LPI_DMIC3_CLK clock LPI_DMIC3_DATA...
  • Page 29 Smart Module Series SD Card Interface Pin Name Pin No. Description DC Characteristics Comment SD_CLK SD card clock 1.8 V SD card: SD_CMD SD card command max = 0.58 V SD_DATA0 SDIO data bit 0 min = 1.27 V max = 0.45 V SD_DATA1 SDIO data bit 1 min = 1.4 V...
  • Page 30 Smart Module Series PCIE1_RX1_M PCIe1 receive 1 (-) PCIE1_WAKE_N PCIe1 wake up host PCIE1_RST_N PCIe1 reset PCIE1_CLKREQ_N PCIe1 clock request PCIe2 reference PCIE2_REFCLK_P clock (+) PCIe2 reference PCIE2_REFCLK_M clock (-) PCIE2_TX0_P PCIe2 transmit 0 (+) PCIE2_TX0_M PCIe2 transmit 0 (-) PCIE2_RX0_P PCIe2 receive 0 (+) 85 Ω...
  • Page 31 Smart Module Series TP1_I2C_SDA TP1 I2C data LCM Interfaces Pin Name Pin No. Description DC Characteristics Comment Current output for LCD_BL_A LCD backlight Current sink for LCD LCD_BL_K1 backlight Current sink for LCD LCD_BL_K2 backlight Current sink for LCD LCD_BL_K3 backlight Current sink for LCD LCD_BL_K4...
  • Page 32 Smart Module Series LCD0 MIPI lane 3 DSI0_LN3_N data (-) DSI1_CLK_P LCD1 MIPI clock (+) DSI1_CLK_N LCD1 MIPI clock (-) LCD1 MIPI lane 0 DSI1_LN0_P data (+) LCD1 MIPI lane 0 DSI1_LN0_N data (-) LCD1 MIPI lane 1 DSI1_LN1_P data (+) LCD1 MIPI lane 1 DSI1_LN1_N data (-)
  • Page 33 Smart Module Series MIPI lane 3 data of CSI0_LN3_N camera 0 (-) MIPI clock of camera CSI1_CLK_P 1 (+) MIPI clock of camera CSI1_CLK_N 1 (-) MIPI lane 0 data of CSI1_LN0_P camera 1 (+) MIPI lane 0 data of CSI1_LN0_N camera 1 (-) MIPI lane 1 data of...
  • Page 34 Smart Module Series MIPI clock of camera CSI3_CLK_N 3 (-) MIPI lane 0 data of CSI3_LN0_P camera 3 (+) MIPI lane 0 data of CSI3_LN0_N camera 3 (-) MIPI lane 1 data of CSI3_LN1_P camera 3 (+) MIPI lane 1 data of CSI3_LN1_N camera 3 (-) MIPI lane 2 data of...
  • Page 35 Smart Module Series MIPI lane 0 data of CSI5_LN0_N camera 5 (-) MIPI lane 1 data of CSI5_LN1_P camera 5 (+) MIPI lane 1 data of CSI5_LN1_N camera 5 (-) MIPI lane 2 data of CSI5_LN2_P camera 5 (+) MIPI lane 2 data of CSI5_LN2_N camera 5 (-) MIPI lane 3 data of...
  • Page 36 Smart Module Series CCI1_I2C_SDA I2C data of CCI1 CCI1_I2C_SCL I2C clock of CCI1 CCI2_I2C_SDA I2C data of CCI2 CCI2_I2C_SCL I2C clock of CCI2 CCI3_I2C_SDA I2C data of CCI3 CCI3_I2C_SCL I2C3 clock of CCI3 CCI_I3C_SDA I3C data of CCI CCI_I3C_SCL I3C clock of CCI Power supply for DVDD of camera.
  • Page 37 Smart Module Series Power supply for DOVDD of camera. Vnom = 1.8 V Add a 4.7 μF bypass capacitor if LDO7F_1V8 1.8 V output max = 600 mA used. If unused, keep this pin open. Flashlight Interfaces Pin Name Pin No. Description DC Characteristics Comment...
  • Page 38 Smart Module Series DCE request to send UART16_RTS signal to DTE UART17_TXD UART17 transmit UART17_RXD UART17 receive DCE clear to send UART17_CTS signal from DTE DCE request to send UART17_RTS signal to DTE Sensor Interfaces Pin Name Pin No. Description DC Characteristics Comment I2C clock for external...
  • Page 39 Smart Module Series SPI2_CS SPI2 chip select SPI2 master-in SPI2_MISO slave-out SPI2 master-out SPI2_MOSI slave-in SPI4_CLK SPI4 clock SPI4_CS SPI4 chip select SPI4 master-in SPI4_MISO slave-out SPI4 master-out SPI4_MOSI slave-in FP_SPI14_CLK FP SPI14 clock FP_SPI14_CS FP SPI14 chip select FP SPI14 master-in FP_SPI14_MISO slave-out FP SPI14 master-out...
  • Page 40 Smart Module Series 2.4 GHz WWAN & COEX_RXD Wi-Fi/Bluetooth If unused, connect it to GND. coexistence receive 2.4 GHz WWAN & If unused, connect it to GND COEX_TXD Wi-Fi/Bluetooth with 10 kΩ resistor. coexistence transmit NFC Interface Pin Name Pin No. Description DC Characteristics Comment...
  • Page 41 Smart Module Series General-purpose PM_ADC4 ADC interface 4 Charging Interface Pin Name Pin No. Description DC Characteristics Comment Battery voltage BAT_P Must be connected. detect (+) Battery voltage BAT_M Must be connected. detect (-) Sensed battery VBAT_SNS_M voltage (-) for Must be connected.
  • Page 42 Smart Module Series Vibration Drive Interface Pin Name Pin No. Description DC Characteristics Comment Haptics driver output HAP_P Haptics driver output HAP_M HAP_PWM_IN Haptics PWM input If unused, connect it to GND. Power supply for VDD_HAP haptics HAP_BOOST_EN Haptics boost enable Other Interfaces Pin Name Pin No.

  • Page 43: Evb Kit

    Smart Module Series 2.6. EVB Kit To help you develop applications with the module, Quectel supplies an evaluation board with accessories to control or test the module. For more details, see document [1]. SG865W_Series_Hardware_Design 42 / 117...

  • Page 44: Operating Characteristics

    Smart Module Series Operating Characteristics 3.1. Power Supply 3.1.1. Power Supply Pins The module provides 5 VBAT pins, 4 VPH_PWR pins. VBAT pins must be connected to an external power to supply power to the module. VPH_PWR pins are used to power other devices. 3.1.2.
  • Page 45 Smart Module Series BAT_ID Battery type detect SMB1390 parallel charging SMB_THERM temperature detect SMB1390 parallel charging Parallel charging is not SMB_STATUS status indicator supported by default. If parallel charging is not SMB1390 parallel charging SMB_EN_CHG enable needed, keep these pins open.

  • Page 46: Reference Design For Power Supply

    Smart Module Series unable to detect the battery, making the battery cannot be charged. BAT_P and BAT_M must be connected, and VBAT_SNS_M pin must be connected. Otherwise, the module will have abnormalities in voltage detection, as well as associated module power on/off and battery charging and discharging issues.
  • Page 47 Smart Module Series Input current 3.8 V Voltage Figure 5: Voltage Drop Sample To prevent the voltage from dropping below 3.1 V, use a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω), and reserve a multi-layer ceramic chip capacitor (MLCC) array due to its ultra-low ESR. It is recommended to use four ceramic capacitors (10 μF, 100 nF, 33 pF, 10 pF) to compose the MLCC array, and place four capacitors close to VBAT pins.

  • Page 48: Turn On

    Smart Module Series 3.2. Turn On 3.2.1. Turn On with PWRKEY Table 8: Pin Definition of PWRKEY Pin Name Pin No. Description Comment PWRKEY Turn on/off the module PWRKEY pin is pulled to 1.8 V internally. The module can be turned on by driving PWRKEY low for at least 1.6 s. It is recommended to use an open drain/collector driver to control the PWRKEY.

  • Page 49: Turn On Automatically With Cbl_Pwr_N

    Smart Module Series PWRKEY Turn-on pulse M odul e Close to S1 Figure 8: Turn On the Module Using a Button 3.2.2. Turn On Automatically with CBL_PWR_N Table 9: Pin Definition of CBL_PWR_N Pin Name Pin No. Description CBL_PWR_N Initiates power-on when grounded The module can be turned on automatically by driving CBL_PWR_N pin to GND via a 1 kΩ...

  • Page 50: Turn Off/Restart

    Smart Module Series The power-up timing is illustrated in the following figure. NOTE 2 VBAT (Typ: 3.8 V) PWRKEY > 1.6 s 50 ms VREG_BOB Software controlled Software VREG_S4A_1V8 controlled LDO12A_1V8 38 s Others Active Figure 10: Power-up Timing NOTE 1.

  • Page 51: Vrtc Interface

    Smart Module Series VBAT > 8 s PWRKEY Others Power down Figure 11: Forced Power-down Timing 3.4. VRTC Interface The RTC (Real Time Clock) can be powered by an external power source through VRTC when the module is powered down and there is no power supply for the VBAT. The external power source can be a capacitor according to application demands.

  • Page 52: Power Supply Output

    Smart Module Series ⚫ When VBAT is disconnected, the recommended input voltage range for VRTC is 2.5–3.25 V and the recommended typical value is 3.0 V. ⚫ When powered by VBAT, the RTC error is 50 ppm. When powered by VRTC, the RTC error is about 200 ppm.
  • Page 53 Smart Module Series NOTE The actual LDO output voltage can be adjusted according to different application scenarios. SG865W_Series_Hardware_Design 52 / 117...

  • Page 54: Application Interfaces

    Smart Module Series Application Interfaces 4.1. USB Interfaces USB0 interface: ⚫ Compliant with the USB 3.1 Gen 2 and USB 2.0 specifications ⚫ Supports USB OTG function ⚫ Supports host and device modes ⚫ Used for AT command communication, data transmission, software debugging and firmware upgrade ⚫...
  • Page 55 Smart Module Series USB0 3.1 channel 0 SuperSpeed USB0_SS0_TX_M transmit (-) USB0 3.1 channel 1 SuperSpeed USB0_SS1_RX_P receive (+) USB0 3.1 channel 1 SuperSpeed USB0_SS1_RX_M receive (-) USB0 3.1 channel 1 SuperSpeed USB0_SS1_TX_P transmit (+) USB0 3.1 channel 1 SuperSpeed USB0_SS1_TX_M transmit (-) USB_CC1...

  • Page 56: Usb0 Type-C

    Smart Module Series 4.1.1. USB0 Type-C USB Type-C Module USB_VBUS VBUS USB0_DP USB0_DM USB_CC1 USB_CC2 USB_SBU1 SBU1 SBU2 USB_SBU2 USB0 _ SS0 _RX_P RX1+ _ SS0 _RX_M USB0 RX1- _ SS0 _TX_P USB0 TX1+ _ SS0 _TX_M TX1- USB0 _ SS1 _RX_P USB0 RX2+ _ SS1 _RX_M...

  • Page 57: Displayport

    Smart Module Series USB0_SS0_RX_M 18.63 USB0_SS0_TX_P 22.72 0.29 USB0_SS0_TX_M 22.43 USB0_SS1_RX_P 22.03 -0.22 USB0_SS1_RX_M 22.25 USB0_SS1_TX_P 24.18 -0.21 USB0_SS1_TX_M 24.39 DP_AUX_P 19.17 -0.42 DP_AUX_M 19.59 USB1_DP 18.47 USB1_DM 18.17 USB1_SS_TX_P 20.81 -0.07 USB1_SS_TX_M 20.88 USB1_SS_RX_P 14.82 -0.25 USB1_SS_RX_M 15.07 4.1.2. DisplayPort The module supports 4-lane DisplayPort mode of up to 4K @ 60 fps over Type-C.
  • Page 58 Smart Module Series DP_AUX_P/M SBU1/2 DP_AUX_P/N USB0_DP/M USB1_DP/M USB1_DP/M USB_CC1/CC2 USB_CC1/CC2 HOTPLUG_DET/VCONN USB_VBUS USB_VBUS USB_VBUS UART5_CTS SBU_SW_OE UART5_RTS SBU_SW_SEL The reference design for DisplayPort is shown below: USB_VBUS USB_VBUS USB0_DM USB0_DP USB_CC1 USB_CC2 USB0 _ SS0 _RX_P RX1+ USB0 _ SS0 _RX_M RX1 - USB0 _ SS0 _TX_P TX1+...

  • Page 59: Uart Interfaces

    Smart Module Series 4.2. UART Interfaces The module provides 4 UART interfaces: ⚫ UART5/UART16/UART17: 4-wire UART interface, supports hardware flow control. ⚫ Debug UART: 2-wire UART interface; used for debugging by default, baud rate is 115200 bps by default. Pin definition of the UART interfaces is here as follows: Table 14: Pin Definition of UART Interfaces Pin Name Pin No.
  • Page 60 Smart Module Series VREG_S4A_1V8 VCCB VDD_3.3V VCCA 100 pF 100 pF CTS_3.3V UART 5_ CTS UART 5_ RTS RTS_3.3V TXS0104EPWR UART5_ TXD TXD_3.3V UART5_ RXD RXD_3.3V Figure 16: Reference Circuit with Voltage-level Translator Chip (for UART 5) When the module communicates with PC, voltage-level translator is also required. A voltage-level translator chip and an RS-232 translator chip are recommended to be added.

  • Page 61: Sd Card Interface

    Smart Module Series 4.3. SD Card Interface The module supports SD 3.0 specifications. The pin definition of the SD card interface is shown below. Table 15: Pin Definition of SD Card Interface Pin Name Pin No. Description Comment SD_CLK SD card clock SD_CMD SD card command SD_DATA0...
  • Page 62 Smart Module Series SD_LDO6C VREG_S4A_1V8 SD_LDO9C 120K NM_51K NM_51K NM_10K NM_51K NM_51K SD_DATA2 P1-DAT2 P2-CD/DAT3 SD_DATA3 P3-CMD SD_CMD P4-VDD SD_CLK P5-CLK P6-VSS SD_DATA0 P7-DAT0 SD_DATA1 P8-DAT1 DETECTIVE SD_DET Module 2.2 μF 10 pF SD Card Connector Figure 18: Reference Circuit for SD Card Interface SD_LDO9C is a peripheral driver power supply for SD card.

  • Page 63: Gpios

    Smart Module Series SD_DATA1 23.82 SD_DATA2 23.4 SD_DATA3 22.57 4.4. GPIOs The module has abundant GPIO interfaces with 1.8 V power domain. The pin definition is listed below. Table 17: Pin Definition of GPIO Interfaces Pin Name Pin No. Description Comment GPIO56 General-purpose input/output...

  • Page 64: I2C Interfaces

    Smart Module Series 4.5. I2C Interfaces The module provides 9 I2C interfaces. All I2C interfaces are open drain signals and therefore you must pull them up externally. The reference power domain is 1.8 V. Table 18: Pin Definition of I2C Interfaces Pin Name Pin No.

  • Page 65: Adc Interfaces

    Smart Module Series 4.6. ADC Interfaces The module provides 4 Analog-to-Digital Converter (ADC) interfaces. To improve the accuracy of ADC, the trace of ADC interfaces should be surrounded by ground. Table 19: Pin Definition of ADC Interface Pin Name Pin No. Description Comment PM_ADC1...

  • Page 66: Pcie Interfaces

    Smart Module Series 3. It is recommended to use resistor divider circuit for ADC application. 4.7. PCIe Interfaces The module provides 2 integrated PCIe (Peripheral Component Interconnect Express) interfaces. The key features of the PCIe interfaces are mentioned below: ⚫ PCI Express Base Specification Revision 3.0 compliance.
  • Page 67 Smart Module Series PCIE2_TX0_P PCIe2 transmit 0 (+) PCIE2_TX0_M PCIe2 transmit 0 (-) PCIE2_RX0_P PCIe2 receive 0 (+) PCIE2_RX0_M PCIe2 receive 0 (-) PCIE2_TX1_P PCIe2 transmit 1 (+) PCIE2_TX1_M PCIe2 transmit 1 (-) PCIE2_RX1_P PCIe2 receive 1 (+) PCIE2_RX1_M PCIe2 receive 1 (-) PCIE2_WAKE_N PCIe2 wake up host PCIE2_RST_N...
  • Page 68 Smart Module Series NOTE The reference design of PCIe2 interface is similar to PCIe1 interface. The following principles of PCIe interface design should be complied with to meet PCIe specifications. ⚫ It is important to route the PCIe signal traces as differential pairs with ground surrounded. The differential impedance is 70–100 Ω...

  • Page 69: Vibrator Drive Interface

    Smart Module Series PCIE1_RX0_M 22.25 PCIE1_TX1_P 17.06 0.09 PCIE1_TX1_M 16.97 PCIE1_RX1_P 23.58 -0.24 PCIE1_RX1_M 23.82 PCIE2_REFCLK_P 19.38 -0.28 PCIE2_REFCLK_M 19.66 PCIE2_TX0_P 22.19 0.35 PCIE2_TX0_M 21.84 PCIE2_RX0_P 19.19 -0.24 PCIE2_RX0_M 19.43 PCIE2_TX1_P 19.84 0.18 PCIE2_TX1_M 19.66 PCIE2_RX1_P 16.49 -0.02 PCIE2_RX1_M 16.51 4.8.

  • Page 70: Wireless Charging Interface

    Smart Module Series VDD_HAP Power supply for haptics HAP_BOOST_EN Haptics boost enable The vibrator is driven by an exclusive circuit, and a reference design is shown below. VPH_PWR HAP_BOOST_EN BOOST IC VDD_HAP HAP_P VIB+ 33 pF VIB- HAP_M Motor 33 pF Module Figure 20: Reference Design for Vibrator Connection 4.9.

  • Page 71: Rgb Interfaces

    Smart Module Series 4.10. RGB Interfaces The module provides 3 RGB interfaces, which are with maximal output current up to 12 mA. Table 25: Pin Definition of RGB Interfaces Pin Name Pin No. Description R_LED Current source for red LED G_LED Current source for green LED B_LED...

  • Page 72: Lcm Interfaces

    Smart Module Series VOL_DOWN Volume down 4.12. LCM Interfaces The module provides 2 LCM interfaces, which is MIPI_DSI standard compliant. The interface supports high-speed differential data transmission and supports double 2560 × 1600 @ 60 fps with 4-lane MIPI or 5040 ×...
  • Page 73 Smart Module Series DSI0_LN2_P LCD0 MIPI lane 2 data (+) DSI0_LN2_N LCD0 MIPI lane 2 data (-) DSI0_LN3_P LCD0 MIPI lane 3 data (+) DSI0_LN3_N LCD0 MIPI lane 3 data (-) DSI1_CLK_P LCD1 MIPI clock (+) DSI1_CLK_N LCD1 MIPI clock (-) DSI1_LN0_P LCD1 MIPI lane 0 data (+) DSI1_LN0_N...
  • Page 74 Smart Module Series VPH_PWR LDO14A_1V8 LCD_BL_A LEDA LCD_BL_K1 LEDK LCD_BL_K2 LCD0 _TE LPTE RESET LCD0 _ RST LCD_ID PM_ADC1 NC (SDA-TP) LDO11C_3V1 NC (SCL-TP) NC (RST-TP) 1μF NC (EINT-TP) LDO_IC GPIO 100K 4.7 μ F 100 nF VIO18 2.2 μ F 2.2 μ...

  • Page 75: Touch Panel Interfaces

    Smart Module Series ⚫ Use the high voltage output (LCD_BL_A) for powering WLED strings, and the output OVP voltage is 32.5 V. ⚫ Support 4 current sinks (LCD_BL_K1, LCD_BL_K2, LCD_BL_K3, LCD_BL_K4), with maximum sink current up to 30 mA for each string. ⚫...

  • Page 76: Camera Interfaces

    Smart Module Series LDO1C_1V8 LDO13A_3V0 2.2K 2.2K TP0_I2C_SDA TP0_I2C_SCL TP0_RST RESET TP0_INT 4.7 μF 100 nF Module Figure 23: Reference Design for TP0 Interface NOTE The reference design of TP1 interface is similar to TP0 interface. 4.14. Camera Interfaces Based on the standard MIPI CSI video input interface, the module supports 7 cameras, and the maximum pixel of the camera can be up to 64 MP.
  • Page 77 Smart Module Series MIPI lane 2 data of CSI0_LN2_P camera 0 (+) MIPI lane 2 data of CSI0_LN2_N camera 0 (-) MIPI lane 3 data of CSI0_LN3_P camera 0 (+) MIPI lane 3 data of CSI0_LN3_N camera 0 (-) CSI1_CLK_P MIPI clock of camera 1 (+) CSI1_CLK_N MIPI clock of camera 1 (-)
  • Page 78 Smart Module Series MIPI lane 3 data of CSI2_LN3_P camera 2 (+) MIPI lane 3 data of CSI2_LN3_N camera 2 (-) CSI3_CLK_P MIPI clock of camera 3 (+) CSI3_CLK_N MIPI clock of camera 3 (-) MIPI lane 0 data of CSI3_LN0_P camera 3 (+) MIPI lane 0 data of...
  • Page 79 Smart Module Series CSI5_CLK_P MIPI clock of camera 5 (+) CSI5_CLK_N MIPI clock of camera 5 (-) MIPI lane 0 data of CS5_LN0_P camera 5 (+) MIPI lane 0 data of CSI5_LN0_N camera 5 (-) MIPI lane 1 data of CSI5_LN1_P camera 5 (+) MIPI lane 1 data of...
  • Page 80 Smart Module Series CCI0_I2C_SCL I2C clock of CCI0 CCI1_I2C_SDA I2C data of CCI1 CCI1_I2C_SCL I2C clock of CCI1 CCI2_I2C_SDA I2C data of CCI2 CCI2_I2C_SCL I2C clock of CCI2 CCI3_I2C_SDA I2C data of CCI3 CCI3_I2C_SCL I2C3clock of CCI3 CCI_I3C_SDA I3C data of CCI CCI_I3C_SCL I3C clock of CCI Power supply for DVDD of...
  • Page 81 Smart Module Series If unused, keep this pin open. Power supply for DOVDD of camera. Add a 4.7 μF bypass capacitor if LDO7F_1V8 1.8 V output used. If unused, keep this pin open. The following is a reference circuit design for camera applications. CAM0_AF_VDD AFVDD LDO5F_2V85...

  • Page 82: Design Considerations

    Smart Module Series LDO7C_2V85 VPH_PWR CAM0_AF_VDD_2V8 LDO_IC CAM0_AFVDD_EN 2.2 μ F Module 2.2 μ F 100K Figure 25: Reference Design of Camera Power Supply NOTE CAM0_AFVDD_EN pin can be multiplexed from UART17_CTS. 4.14.1. Design Considerations ⚫ Special attention should be paid to the pin definition of LCM/camera connectors. Assure the module and the connectors are correctly connected.
  • Page 83 Smart Module Series Table 30: MIPI Trace Length Inside the Module Signal Pin No. Length (mm) Length Difference (mm) DSI0_CLK_P 22.56 0.15 DSI0_CLK_N 22.41 DSI0_LN0_P 22.80 -0.24 DSI0_LN0_N 23.04 DSI0_LN1_P 22.85 0.31 DSI0_LN1_N 22.54 DSI0_LN2_P 22.40 -0.17 DSI0_LN2_N 22.57 DSI0_LN3_P 22.89 0.04 DSI0_LN3_N...
  • Page 84 Smart Module Series CSI0_LN0_N 18.73 CSI0_LN1_P 18.78 0.08 CSI0_LN1_N 18.70 CSI0_LN2_P 19.89 0.34 CSI0_LN2_N 19.55 CSI0_LN3_P 19.25 -0.12 CSI0_LN3_N 19.37 CSI1_CLK_P 18.14 -0.06 18.2 CSI1_CLK_N 18.57 CSI1_LN0_P 0.26 18.31 CSI1_LN0_N 18.08 CSI1_LN1_P -0.09 CSI1_LN1_N 18.17 CSI1_LN2_P 17.87 0.24 CSI1_LN2_N 17.63 CSI1_LN3_P 18.84 0.08...
  • Page 85 Smart Module Series CSI2_LN3_P 14.83 CSI2_LN3_N 14.53 CSI3_CLK_P 31.35 -0.28 CSI3_CLK_N 31.63 CSI3_LN0_P 30.96 -0.12 CSI3_LN0_N 31.08 CSI3_LN1_P 31.16 0.22 CSI3_LN1_N 30.94 30.94 CSI3_LN2_P -0.04 30.98 CSI3_LN2_N 31.86 CSI3_LN3_P 0.25 31.61 CSI3_LN3_N CSI4_CLK_P 14.90 0.23 CSI4_CLK_N 14.67 CSI4_LN0_P 15.38 0.07 CSI4_LN0_N 15.31 CSI4_LN1_P...
  • Page 86 Smart Module Series CSI5_LN0_N 19.27 CSI5_LN1_P 18.92 0.28 CSI5_LN1_N 18.64 CSI5_LN2_P 18.65 -0.02 CSI5_LN2_N 18.67 CSI5_LN3_P 19.26 -0.19 CSI5_LN3_N 19.45 Table 31: CSI and DSI Data Rate and Max. Trace Length (D-PHY) Data Rate Total Insertion Loss (dB) Cable Insertion Loss (dB) Max.

  • Page 87: Flashlight Interfaces

    Smart Module Series 4.14.2. Flashlight Interfaces The module supports 3 flash LED drivers, FLASH_LED1 and FLASH_LED2 are both with maximal output current up to 1.5 A per channel in flash mode and 300 mA in torch mode. FLASH_LED3 with maximal output current up to 0.75 A in flash mode and 300 mA in torch mode.

  • Page 88: Audio Interfaces

    Smart Module Series Table 33: Pin Definition of Sensor Interfaces Pin Name Pin No. Description SENSOR_I2C_SDA I2C clock for external sensor SENSOR_I2C_SCL I2C data for external sensor SENSOR_I3C_SDA I3C data for external sensor SENSOR_I3C_SCL I3C clock for external sensor SENSOR_SPI_CLK SPI clock for external sensor SENSOR_SPI_CS SPI chip select for external sensor...

  • Page 89: I2S Interfaces

    Smart Module Series WSA_SWR_DATA WSA SoundWire data WCD_RST WCD reset WCD_SWR_TX_CLK WCD SoundWire transmit clock WCD_SWR_TX_DATA0 WCD SoundWire transmit data 0 WCD_SWR_TX_DATA1 WCD SoundWire transmit data 1 WCD_SWR_RX_CLK WCD SoundWire receive clock WCD_SWR_RX_DATA0 WCD SoundWire receive data 0 WCD_SWR_RX_DATA1 WCD SoundWire receive data 1 LPI_DMIC3_CLK LPI digital MIC3 clock LPI_DMIC3_DATA...

  • Page 90: Spi Interfaces

    Smart Module Series MI2S0_DATA1 MI2S0 data channel 1 MI2S2_SCLK MI2S2 bit clock MI2S2_WS MI2S2 word select MI2S2_DATA0 MI2S2 data channel 0 MI2S2_DATA1 MI2S2 data channel 1 4.18. SPI Interfaces The module provides 5 SPI interfaces. These interfaces can only support the master mode. SPI interfaces can be used for fingerprint recognition.

  • Page 91: Usb_Boot

    Smart Module Series NFC_SE_SPI8_MISO NFC SE SPI8 master-in slave-out NFC_SE_SPI8_MOSI NFC SE SPI8 master-out slave-in SENSOR_SPI_CLK SPI clock for external sensor SENSOR_SPI_CS SPI chip select for external sensor SENSOR_SPI_MOSI SPI master-out slave-in for external sensor SENSOR_SPI_MISO SPI master-in slave-out for external sensor 4.19.

  • Page 92: Rf Specifications

    Smart Module Series RF Specifications 5.1. RF Antenna Interface This module provides 3 antennas, one of which is Wi-Fi/Bluetooth antenna (Wi-Fi and Bluetooth functions share the same antenna), one antenna is single Wi-Fi and one antenna is reserved for Bluetooth. The interface impedance is 50 Ω.

  • Page 93: Rf Performance

    Smart Module Series Wi-Fi/Bluetooth antenna ANT_WIFI0/ ANT_WIFI1/ ANT_BT Module Figure 28: Reference Design for Wi-Fi/Bluetooth Antenna Interface NOTE The dedicated Bluetooth antenna circuit should be reserved for future debugging. 5.2. RF Performance Table 38: Pin Definition of Wi-Fi/Bluetooth Application Interfaces Pin Name Pin No.

  • Page 94: Wi-Fi Overview

    Smart Module Series Table 39: Wi-Fi/Bluetooth Frequency Type Frequency Unit 2402 – 2482 Wi-Fi 5170–5835 BLE 5.1 2402–2480 5.2.1. Wi-Fi Overview The module supports 2.4 GHz and 5 GHz double-band WLAN wireless communication based on IEEE 802.11a/b/g/n/ac/ax standard protocols. The maximum data rate is up to 1774.5 Mbps (2 × 2 + 2 × 2 11ax DBS).
  • Page 95 Smart Module Series 802.11a 54 Mbps 15 dBm ± 2.5 dB 802.11n HT20 MCS0 18 dBm ± 2.5 dB 802.11n HT20 MCS7 15 dBm ± 2.5 dB 802.11n HT40 MCS0 18 dBm ± 2.5 dB 802.11n HT40 MCS7 15 dBm ± 2.5 dB 802.11ac VHT20 MCS0 18 dBm ±...
  • Page 96 Smart Module Series 802.11n HT20 MCS7 -73 dBm 802.11n HT40 MCS0 -90 dBm 802.11n HT40 MCS7 -69 dBm 802.11ax HE20 MCS0 -93 dBm 802.11ax HE20 MCS11 -64 dBm 802.11ax HE40 MCS0 -92 dBm 802.11ax HE40 MCS11 -62 dBm 802.11a 6Mbps -95 dBm 802.11a 54Mbps...

  • Page 97: Bluetooth Overview

    Smart Module Series NOTE The module conforms to the IEEE specifications. 5.2.2. Bluetooth Overview The module supports Bluetooth 5.1 (BR/EDR + BLE) specification, as well as GFSK, 8-DPSK, Π/4-DQPSK modulation modes. The BR/EDR channel bandwidth is 1 MHz, and can accommodate 79 channels. The BLE channel bandwidth is 2 MHz, and can accommodate 40 channels.

  • Page 98: Reference Design Of Rf Routing

    Smart Module Series 5.3. Reference Design of RF Routing For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S).

  • Page 99: Antenna Design Requirements

    Smart Module Series Figure 32: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, follow the principles below in RF layout design : ⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.

  • Page 100: Rf Connector Recommendation

    Smart Module Series ⚫ Input impedance: 50 Ω ⚫ Polarization type: Vertical ⚫ Cable insertion loss: < 1 dB 5.5. RF Connector Recommendation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by Hirose. Figure 33: Dimensions of the Receptacle (Unit: mm) U.FL-LP series mated plugs listed in the following figure can be used to match the U.FL-R-SMT connector.
  • Page 101 Smart Module Series Figure 34: Specifications of Mated Plugs The following figure describes the space factor of mated connectors. Figure 35: Space Factor of Mated Connectors (Unit: mm) For more details, visit http://www.hirose.com. SG865W_Series_Hardware_Design 100 / 114...

  • Page 102: Electrical Characteristics & Reliability

    Smart Module Series Electrical Characteristics & Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings voltage on digital and analog pins of the module are listed in the following table. Table 44: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT -0.3 USB_VBUS -0.3 Voltage at Digital Pins...

  • Page 103: Power Consumption

    Smart Module Series 6.3. Power Consumption Table 46: SG865W-WF Power Consumption Description Conditions Typ. Unit μA OFF state Power off Sleep state Enter standby after power on Table 47: SG865W-AP Power Consumption Description Conditions Typ. Unit μA OFF state Power off Sleep state Enter standby after power on 6.4.

  • Page 104: Esd Protection

    Smart Module Series 6.5. ESD Protection Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design.

  • Page 105: Mechanical Information

    Smart Module Series Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ± 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 36: Module Top and Side Dimensions SG865W_Series_Hardware_Design 104 / 114...
  • Page 106 Smart Module Series Figure 37: Module Bottom Dimensions (Bottom View) ⚫ NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. SG865W_Series_Hardware_Design 105 / 114...

  • Page 107: Recommended Footprint

    Smart Module Series 7.2. Recommended Footprint Figure 38: Recommended Footprint (Top View) NOTE Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. SG865W_Series_Hardware_Design 106 / 114...

  • Page 108: Top And Bottom Views

    Figure 39: Top and Bottom Views of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. SG865W_Series_Hardware_Design 107 / 114...

  • Page 109: Storage, Manufacturing & Packaging

    Smart Module Series Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: the temperature should be 23 ± 5 ° C and the relative humidity should be 35–60 %.

  • Page 110: Manufacturing And Soldering

    Smart Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3.
  • Page 111 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 3. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [4].

  • Page 112: Packaging Specifications

    Smart Module Series 8.3. Packaging Specifications The module adopts carrier tape packaging and details are as follow: 8.3.1. Carrier Tape Dimension details are as follow: Figure 41: Carrier Tape Dimension Drawing Table 52: Carrier Tape Dimension Table (Unit: mm) 42.6 46.6 4.25 5.25...

  • Page 113: Packaging Process

    Smart Module Series Table 53: Plastic Reel Dimension Table (Unit: mm) øD1 øD2 72.5 8.3.3. Packaging Process Place the module into the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape to the plastic reel and use the protective tape for protection.

  • Page 114: Appendix References

    Smart Module Series Appendix References Table 54: Related Documents Document Name [1] Quectel_SA800U-WF_EVB_User_Guide [2] Quectel_ SG865W_Series _GPIO_Configuration [3] Quectel_RF_Layout_Application_Note [4] Quectel_Module_Secondary_SMT_Application_Note Table 55: Terms and Abbreviations Abbreviation Description Analog-to-Digital Converter Artificial Intelligence Application Processor Bluetooth Low Energy Bits Per Second BPSK Binary Phase Shift Keying Date Base System...
  • Page 115 Smart Module Series Data Communications Equipment Double Data Rate Downlink Data Processing Unit Digital Signal Processor Data Terminal Equipment Data Terminal Ready Enhanced Data Rate Enhanced Full Rate Electromagnetic Interference Eccentric Rotating Machines Electrostatic Discharge Equivalent Series Resistance Frequency Division Duplex Front-End Module Fingerprint Full Rate...
  • Page 116 Smart Module Series IEEE Institute of Electrical and Electronics Engineers Input/Output Image Signal Processing Inom Nominal Current License Assisted Access Low Band Liquid Crystal Display Liquid Crystal Monitor Light Emitting Diode Low-dropout Regulator Land Grid Array Linear Resonant Actuators Low Power Island Media Access Control MIMO Multiple Input Multiple Output...
  • Page 117 Smart Module Series Personal Computer Printed Circuit Board PCIe Peripheral Component Interconnect Express Pulse Code Modulation Personal Digital Assistant Protocol Data Unit Physical Layer PMIC Power Management Integrated Circuit Point of Sale Pulse Width Modulation Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying Ring Indicator Radio Frequency RoHS...
  • Page 118 Smart Module Series Transmit UART Universal Asynchronous Receiver/Transmitter Universal Flash Storage Uplink UMTS Universal Mobile Telecommunications System Unsolicited Result Code Universal Serial Bus VBAT Voltage at Battery (Pin) Vmax Maximum Voltage Vnom Nominal Voltage Vmin Minimum Voltage Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage...
  • Page 119 Smart Module Series Wi-Fi Wireless Fidelity WWAN Wireless Wide Area Network SG865W_Series_Hardware_Design 118 / 114...

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