Lcm Interface - Quectel SG560D Series Hardware Design

4.11. LCM Interface

The module provides one LCM interface based on MIPI_DSI standard. The interface supports one group
of 4-lane high-speed differential data transmission with maximum speed rate of 2.5 Gbps/lane and
supports FHD + (1200 × 2520 ) @144 fps. The pin definition of the LCM interface is shown below.
Table 26: Pin Definition of LCM Interface
Pin Name Pin No.
PWM1 340
DSI_CLK_P 366
DSI_CLK_N 370
DSI_LN0_P 380
DSI_LN0_N 377
DSI_LN1_P 376
DSI_LN1_N 373
DSI_LN2_P 372
DSI_LN2_N 369
DSI_LN3_P 368
DSI_LN3_N 365
LCD_TE 374
LCD_RST 378
SG560D_Series_Hardware_Design
I/O Description
DO PWM output 1
AO LCD MIPI clock (+)
AO LCD MIPI clock (-)
AO LCD MIPI lane 0 data (+)
AO LCD MIPI lane 0 data (-)
AO LCD MIPI lane 1 data (+)
AO LCD MIPI lane 1 data (-)
AO LCD MIPI lane 2 data (+)
AO LCD MIPI lane 2 data (-)
AO LCD MIPI lane 3 data (+)
AO LCD MIPI lane 3 data (-)
DI LCD tearing effect
DO LCD reset
Smart Module Series
Comment
Backlight control.
Requires differential
impedance of 85 Ω.
1.8 V power domain.
1.8 V power domain.
External pull-up is not
required.
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