Pcie Interface - Quectel EM160R-GL Hardware Design

3.7. PCIe Interface

The module provides one integrated PCIe interface, featuring as follows:
⚫
PCI Express Base Specification Revision 4.0, Version 1.1
⚫
Data rate up to 5 Gbps per lane
Table 13: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PERST#
52 CLKREQ#
EM160R-GL_Hardware_Design
I/O Description
AIO PCIe reference clock (+)
AIO PCIe reference clock (-)
AI PCIe receive data (+)
AI PCIe receive data (-)
AO PCIe transmit data (+)
AO PCIe transmit data (-)
DI PCIe reset input
DO PCIe clock request
LTE-A Module Series
Comment
Requires differential
impedance of 95 Ω.
Requires differential
impedance of 95 Ω.
Requires differential
impedance of 95 Ω.
Active low.
Active low.
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