Quectel SG560D Series Hardware Design page 83

The following is a reference circuit for tri-camera applications.
CAM0_RST
CAM0_MCLK
CCI_I2C_SDA0
CCI_I2C_SCL0
CSI0_LN3_P
CSI0_LN3_N
CSI0_LN2_P
CSI0_LN2_N
CSI0_LN1_P
CSI0_LN1_N
CSI0_LN0_P
CSI0_LN0_N
CSI0_CLK_P
CSI0_CLK_N
CCI_I2C_SDA1
CCI_I2C_SCL1
CAM1_MCLK
CSI1_LN3_P
CSI1_LN3_N
CSI1_LN2_P
CSI1_LN2_N
CSI1_LN1_P
CSI1_LN1_N
CSI1_LN0_P
CSI1_LN0_N
CSI1_CLK_P
CSI1_CLK_N
CAM2_RST
CAM2_MCLK
CSI2_LN3_P
CSI2_LN3_N
CSI2_LN2_P
CSI2_LN2_N
CSI2_LN1_P
CSI2_LN1_N
CSI2_LN0_P
CSI2_LN0_N
CSI2_CLK_P
CSI2_CLK_N
CCI_I2C_SDA2
CCI_I2C_SCL2
Figure 24: Reference Circuit for Three-Camera Applications
SG560D_Series_Hardware_Design
VREG_L5P_2P8
VREG_L4P_2P9
VREG_L2P_1P1
VREG_L6P_1P8
GPIO_12
VREG_L3P_2P8
VREG_L1P_1P05
CAM1_RST
GPIO_32
VREG_L7P_2P8
GPIO_35
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EMI
EMI
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EMI
EMI
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EMI
EMI
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AFVDD
AVDD
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DOVDD
AVDD
DVDD
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AVDD
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DOVDD
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