Pcie Interface - Quectel RG520N-AT Hardware Design

VDD_EXT
0.1 μF
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
Figure 31: Reference Circuit of SPI with a Voltage-level Translator

4.11. PCIe Interface

The module provides one integrated PCIe (Peripheral Component Interconnect Express) interface. The
key features of the PCIe interface are mentioned below:
⚫
PCI Express Specification Revision 3.0 compliance.
⚫
Data rate at 8 Gbps per lane for PCIe 3.0.
⚫
Used to connect to an external Ethernet IC (MAC and PHY) or Wi-Fi IC.
Table 26: Pin Definition of PCIe Interface
Pin Name
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX0_M
PCIE_TX0_P
PCIE_TX1_M
PCIE_TX1_P
PCIE_RX0_M
RG520N-AT_Hardware_Design
VCCA
OE
A1
Translator
A2
A3
A4
NC
Pin No. I/O
40 AIO
38 AIO
44 AO
46 AO
41 AO
43 AO
32 AI
VCCB
0.1 μF
GND
B1
B2
B3
B4
NC
Description
PCIe reference clock (+)
PCIe reference clock (-)
PCIe transmit 0 (-)
PCIe transmit 0 (+)
PCIe transmit 1 (-)
PCIe transmit 1 (+)
PCIe receive 0 (-)
5G Module Series
VDD_MCU
SPI_CS_N_MCU
SPI_CLK_MCU
SPI_MOSI_MCU
SPI_MISO_MCU
Comment
In root complex mode, it is
an output signal.
In endpoint mode, it is an
input signal. Requires
differential impedance of
85 Ω.
Requires differential
impedance of 85 Ω.
If unused, keep them
open.
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