Camera Interfaces - Quectel SG560D Series Hardware Design

A reference design for TP interface is shown below.
TP_I2C_SDA
TP_I2C_SCL
Module

4.13. Camera Interfaces

Based on the MIPI_CSI standard, the module provides four groups of 4-lane MIPI_CSI with maximum
transmission rate of 2.5 Gbps/lane. The module supports two cameras (4-lane + 4-lane), or three
cameras (4-lane + 4-lane + 4-lane), or four cameras (4-lane + 4-lane + 4-lane + 4-lane). The video and
photo quality are determined by various factors such as the camera sensor, camera lens quality.
Table 28: Pin Definition of Camera Interfaces
Pin Name
VREG_L1P_1P05
VREG_L2P_1P1
VREG_L3P_2P8
VREG_L4P_2P9
VREG_L5P_2P8
SG560D_Series_Hardware_Design
LDO18B_1V8
R1
2.2K
TP_RST
TP_INT
D1 D2
GND
Figure 22: Reference Circuit for TP Interface
Pin No. I/O
116 PO
121 PO
113 PO
124 PO
128 PO
LDO7C_3V0
R2
2.2K
D4
D3
C1 C2
4.7 μF 100 nF
Description
DVDD for cameras 1 and 2
DVDD for cameras 0 and 3
AVDD for cameras 1 and 3
AVDD for camera 0
AFVDD for camera 0
Smart Module Series
1
SDA 1.8 V
2
SCL 1.8 V
3
RESET 1.8 V
4
INT 1.8 V
5
GND
6
VDD
D5
TP
Comment
When using
them, it is
recommended
to add bypass
capacitors with
a total
capacitance
not exceeding
45.3 μF.
When using
them, it is
recommended
to add bypass
capacitors with
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