Pcie Interface; Endpoint Mode - Quectel RM502Q-GL Hardware Design

3.8. PCIe Interface

RM502Q-GL provides one integrated PCIe (Peripheral Component Interconnect Express) interface which
complies with the PCI Express Base Specification, Revision 3.0 and supports up to 8 Gbps per lane.
⚫
PCI Express Base Specification Revision 3.0 compliance
⚫
Data rate up to 8 Gbps per lane
The following table shows the pin definition of PCIe interface.
Table 10: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N

3.8.1. Endpoint Mode

RM502Q-GL supports endpoint (EP) mode. In this mode, the module is configured as a PCIe EP device.
The following figure shows a reference circuit of PCIe EP mode.
RM502Q-GL_Hardware_Design
I/O Description
AI/AO PCIe reference clock (+)
AI/AO PCIe reference clock (-)
AI PCIe receive data (+)
AI PCIe receive data (-)
AO PCIe transmit data (+)
AO PCIe transmit data (-)
PCIe reset.
DI
Active LOW.
PCIe clock request.
DO
Active LOW.
PCIe PME wake.
DO
Active LOW.
5G Module Series
RM502Q-GL Hardware Design
Comment
100 MHz. Require differential
impedance of 85 Ω
Require differential impedance
of 85 Ω
Require differential impedance
of 85 Ω
Open drain
Open drain
Open drain
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