Pcie Interface - Quectel LTE-A Series Hardware Design

In addition, RI behavior can be configured flexibly. The default behavior of RI is shown below.
Table 20: Behavior of RI
State Response
Idle RI stays at high level
URC RI outputs 120 ms low pulse when a new URC returns.
The RI behavior can be changed by the AT+QCFG="urc/ri/ring" command. Please refer to document [1]
for details.

3.17. PCIe Interface*

EG060V-EA provides a PCIe interface which is compliant with PCI Express Specification Revision 1.0.
The key features of the PCIe interface are shown below:
⚫
PCI Express Specification Revision 1.0 compliance
⚫
Data rate reaching 2.5 Gbps per lane
⚫
Connection to an external Ethernet IC (MAC and PHY) or WLAN IC.
The following table shows the pin definition of PCIe interface.
Table 21: Pin Definition of PCIe Interface
Pin Name Pin No.
PCIE_REFCLK_P 179
PCIE_REFCLK_M 180
PCIE_TX_M 182
PCIE_TX_P 183
PCIE_RX_M 185
PCIE_RX_P 186
PCIE_CLKREQ_N 188
EG060V-EA_Hardware_Design
I/O Description
Output PCIe reference
AO
clock (+)
Output PCIe reference
AO
clock (-)
AO PCIe transmit (-)
AO PCIe transmit (+)
AI PCIe receive (-)
AI PCIe receive (+)
IO PCIe clock request
LTE-A Module Series
EG060V-EA Hardware Design
Comment
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
In master mode, it is an input signal.
In slave mode, it is an output signal.
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