Pcie Interface; Pcie Operating Mode - Quectel RM500Q-AE Manual

3.7.3.9.

PCIe Interface

RM500Q-AE&RM502Q-AE
Express) interface which complies with the PCI Express Base Specification, Revision 3.0 and supports up
to 8 Gbps per lane.
⚫
PCI Express Base Specification Revision 3.0 compliant
⚫
Data rate up to 8 Gbps per lane
The following table shows the pin definition of PCIe interface.
Table 111110: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N
3.7.1.3.9.1.

PCIe Operating Mode

RM500Q-AE&RM502Q-AE supports endpoint (EP) mode and
module is configured as a PCIe EP device. In RC mode, the module is configured as a PCIe root complex.
The following figure shows a reference circuit for the PCIe interface.
RM500Q-AE&RM502Q-AE_Hardware_Design
modules provides one integrated PCIe (Peripheral Component Interconnect
I/O Description
AI/AO PCIe reference clock (+)
AI/AO PCIe reference clock (-)
AI PCIe receive
AI PCIe receive
AO PCIe transmit
AO PCIe transmit
DI PCIe reset.
DO PCIe clock request.
DO PCIe wake up
RM500Q-AE&RM502Q-AE Hardware Design
Comment
100 MHz. Require differential
impedance of 85 Ω
data (+)
Require differential impedance
of 85 Ω
data (-)
data (+)
Require differential impedance
of 85 Ω
data (-)
Open drain
Active LOW.
Open drain
Active LOW.
Open drain
Active LOW.
root complex (RC) mode. In EP mode, the
5G Module Series
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