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4.13.1.
MIPI Design Considerations
⚫
Special attention should be paid to the pin definition of LCM/camera connectors. Ensure that the
module and the connectors are correctly connected.
⚫
MIPI are high speed signal lines, supporting maximum data rate of 2.5 Gbps/lane. The differential
impedance should be controlled to 85 Ω. Additionally, it is recommended to route the traces on the
inner layer of PCB, and do not cross them with other traces. For the same group of DSI or CSI
signals, keep all MIPI traces of the same length. To avoid crosstalk, a distance of 1.5 times the trace
width among MIPI signal traces is recommended. During impedance matching, do not connect GND
on different planes so as to ensure impedance consistency.
⚫
Make sure the reference ground plane for CSI/DSI is complete and integral without any cut or void.
⚫
Route the camera CLK signals on the inner layer of the PCB and surround them with ground.
⚫
Route CSI and DSI traces according to the following rules:
a)
The intra-pair (P/N) spacing should be equal to the trace width.
b)
The inter-pair spacing should be 1.5 times the trace width.
c)
The spacing relative to other signal lines should be 2.5 times the trace width.
⚫
Route MIPI traces according to the following rules:
Control the differential impedance to 85 Ω ±10 %.
a)
b)
Control intra-lane (P/N) length difference within 0.7 mm.
c)
Control inter-lane length difference within 2.1 mm.
Table 29: Relationship Between CSI Rate and Line Length (D-PHY)
Data Rate
500 Mbps/Lane
750 Mbps/Lane
1.0 Gbps/Lane
1.5 Gbps/Lane
2.1 Gbps/Lane
2.5 Gbps/Lane
SG560D_Series_Hardware_Design
Cable Length (mm)
76.2
152.4
76.2
152.4
76.2
152.4
76.2
152.4
76.2
152.4
76.2
Cable Insertion Loss (dB)
-0.5
-1
-0.7
-1.15
-0.75
-1.4
-0.9
-1.8
-1.3
-2.3
-2.1
Smart Module Series
Line Length (mm)
< 260
< 190
< 210
< 155
< 200
< 125
< 145
< 60
< 170
< 90
< 210
83 / 134
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