Uart Interfaces (J2002/J2003); Pcie To Usb Interface (J1601) - Quectel RG50-Q Series User Manual

3.8. UART Interfaces (J2002/J2003)

The 5G EVB supports two UART interfaces: main UART J2002 and debug UART J2003, supporting baud
rate of 115200 bps by default.
The main UART interface is used for communication between the module and the host application.
The debug UART interface is used for Linux console and log output.
The following figure shows a block diagram of UART interfaces of the EVB.
J2002
Main UART
J2003
Debug UART

3.9. PCIe to USB Interface (J1601)

The 5G EVB reserves a PCIe 3.0 signal over USB interface for developers' testing, and this function is not
enabled by default. Please refer to the following block diagram.
USB3.0 A<->B cable
5G_EVB_User_Guide
U2003
RS232
RS232
Transceiver
U2005
USB to
UART
Bridge
Figure 22: UART Block Diagram
J1601
USB3.0B
WiFi
AP
SEL_1
SEL_2
Figure 23: PCIe Block Diagram
U2001
1.8V
3.3V/1.8V
Level Shift
Q2001 Q2002
1.8V
3.3V/1.8V
Level Shift
U1501/U1701
CLK
TX0/1
PCIe
Switch
RX0/1
5G/LTE-A Module Series
5G EVB User Guide
Module
J0101
J0101
Module
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