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IDT Power Management
Notes
PES4T4 User Manual
turned ON using in-band beacon or out-of-band WAKEN signaling when the traffic resumes). The signal is
sampled High, resulting in retention of the state of the FRSticky bits. The APWRDISN signal input is
sampled again 256 clock cycles after de-assertion of the fundamental reset (PERSTN). A high state of this
signal continues to set the APWREN bit in the SWCTL register.
L2 Mode Disabled
This sequence is shown in Figure 7.3(c). The external POR circuitry ties the APWRDISN signal low. The
APWRDISN signal input is sampled 8 clock cycles after de-assertion of the fundamental reset (PERSTN). A
Low state of this signal results in initialization of the FRSticky bits. The APWRDISN signal input is sampled
again 256 clock cycles after de-assertion of the fundamental reset (PERSTN). A Low state of this signal
resets the APWREN bit in the SWCTL register, thereby disabling L2 mode.
PES4T4 Auxiliary Power Usage
The AUXPD bit in the PCI Express Device Status register is set only when Auxiliary Power Usage is
enabled by either de-asserting the Auxiliary Power Disable active low signal at bring-up time or by setting
the APWREN bit in the Switch Control register. Based on the supported Auxiliary Power Usage model
shown in Figure 7.4, the PES4T4 does not sense an auxiliary power presence on the power pin.
All the core logic in the PES4T4 is powered from a common supply. The auxiliary power is used to
power I/Os that are ON during active standby.
– VA3P3 (3.3V) powers I/Os that are ON during active standby
– VA1P0 (1.0 V)
• Powers RAMBus SerDes Macros
• Powers V
PE
TT
• Powers Core logic that operates during active standby.
Vaux
3.3 V
The auxiliary power supply current budget numbers are given in Tables 7.2 and 7.3.
Regulator
Figure 7.4 Vaux Usage Model
7 - 8
VA3P3
3.3 V
VA1P0
1.0 V
February 1, 2011
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