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IDT Power Management
Notes
PES4T4 User Manual
From State
To State
Any
D0 Uninitialized
D0 Uninitialized
D0 Active
D0 Active
D3
D3
D0 Uninitialized
Hot
D3
D3
Hot
D3
D0 Uninitialized
Cold
Table 7.1 PES4T4 Power Management State Transition Diagram
The PES4T4 PCI-to-PCI bridges (i.e., ports) have the following behavior when in the D3
management state.
– A bridge accepts, processes, and completes all type 0 configuration read and write requests.
– A bridge accepts and processes all message requests that target the bridge.
– All requests received by the bridge on the primary interface, except as noted above, are treated
as unsupported requests (UR).
– Any error message resulting from the receipt of a TLP is reported in the same manner as when
the bridge is not in the D3
– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no
error message is generated).
– All completions that target the bridge are treated as unexpected completions (UC).
– Completions flowing in either direction through the bridge are routed as normal. This behavior of
the bridge does not differ from that of the bridge when it is in the D0 power management state.
– All request TLPs received on the secondary interface are treated as unsupported requests (UR).
PME Messages
Downstream ports (i.e., PCI-PCI bridges associated with downstream ports) support the generation of
hot-plug PME events (i.e., a PM_PME power management message) from the D3
both the case when the downstream port is in the D3
The generation of a PME message by downstream ports necessitates the implementation of a PME
service time-out mechanism to ensure that PME messages are not lost. After a PM_PME message is trans-
mitted, if the PME Status (PMES) bit in the downstream port's PCI Power Management Control and Status
(PMCSR) register is not cleared within the time-out period specified in the PM_PME Time-Out (PMPMETO)
field in the port's PM_PME Timer (PMPMETIMER) register, then the PM_PME message is retransmitted
and the timer is restarted.
If the PES4T4 issues a hot plug PME message but the PME_Status is not cleared before the link enters
a deep sleep state in response to PME_Turn_Off message, it reactivates the link using the wakeup mecha-
nism ( refer to section Wakeup Protocol on page 7-4).
Power-on fundamental reset.
PCI-PCI bridge configured by software.
The Power Management State (PMSTATE) field in the PCI Power
Hot
Management Control and Status (PMCSR) register is written with the
value that corresponds to the D3
The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to D0 state.
Power is removed from the device.
Cold
The device transitions to the D0 Uninitialized state when the system
reinstalls device power and clock and applies a fundamental reset in
response to the Wakeup Protocol. The Wakeup mechanism is pow-
ered by the Vaux power supply.
state (e.g., generation of an ERR_NONFATAL message to the root).
Hot
state or the entire switch is in the D3
Hot
7 - 2
Description
state.
Hot
state. This includes
Hot
state.
Hot
February 1, 2011
power
Hot
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