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IDT Theory of Operation
Notes
PES4T4 User Manual
The PES4T4 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through D)
at each port.
– The value of the INTA, INTB, INTC and INTD aggregated state for the entire switch may be deter-
mined by examining the corresponding field in the upstream port's Interrupt Status (P0_INTSTS)
register.
– The aggregated INTx state for a downstream port may be determined by reading the corre-
sponding field in the port's Interrupt Status (Px_INTSTS) register. This register contains the aggre-
gated state of interrupts generated by that port (i.e., hot-plug) plus interrupt messages received
from the downstream link partner. The interrupt state reflects the state of interrupts as seen by that
port (i.e., before downstream port interrupts are mapped to upstream port interrupts).
An Assert_INTx message is sent to the root by the upstream port (i.e., port 0), when the aggregated
state of the corresponding interrupt in the upstream port transitions from a negated to an asserted state. A
Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre-
sponding interrupt in the upstream port transitions from an asserted to a negated state.
PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port (i.e., port 0). This mapping for the PES4T4 is summarized in Table 3.2.
Downstream
1
Port
Interrupt
Table 3.2 PES4T4 Downstream to Upstream Port Interrupt Routing
1.
Port X INTy corresponds to external downstream generated INTy interrupts and INTy interrupts generated
by the port.
If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are
negated, and the upstream port's aggregate sate is updated accordingly. This may result in the upstream
port generating a Deassert_Intx message.
Upstream Port Interrupt (Port 0)
INTA
INTB
Port 2 INTC
Port 2 INTD
Port 3 INTB
Port 3 INTC
Port 4 INTA
Port 4 INTB
3 - 2
INTC
INTD
Port 2 INTA
Port 2 INTB
Port 3 INTD
Port 3 INTA
Port 4 INTC
Port 4 INTD
February 1, 2011
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