Table 9.2 Upstream Port 0 Configuration Space Registers - Renesas IDT 89HPES4T4 User Manual

IDT Configuration Registers
Notes
PES4T4 User Manual
Upstream Port (Port 0)
Cfg. Register
Size
Offset Mnemonic
0x000 Word P0_VID
0x002 Word P0_DID
0x004 Word P0_PCICMD
0x006 Word P0_PCISTS
0x008 Byte P0_RID
0x009 3 Bytes P0_CCODE
0x00C Byte P0_CLS
0x00D Byte P0_PLTIMER
0x00E Byte P0_HDR
0x00F Byte P0_BIST
0x010 DWord P0_BAR0
0x014 DWord P0_BAR1
0x018 Byte P0_PBUSN
0x019 Byte P0_SBUSN
0x01A Byte P0_SUBUSN
0x01B Byte P0_SLTIMER
0x01C Byte P0_IOBASE
0x01D Byte P0_IOLIMIT
0x01E Word P0_SECSTS
0x020 Word P0_MBASE
0x022 Word P0_MLIMIT
0x024 Word P0_PMBASE
0x026 Word P0_PMLIMIT
0x028 DWord P0_PMBASEU
0x02C DWord P0_PMLIMITU
0x030 Word P0_IOBASEU
0x032 Word P0_IOLIMITU
0x034 Byte P0_CAPPTR
0x038 DWord P0_EROMBASE
0x03C Byte P0_INTRLINE
0x03D Byte P0_INTRPIN
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)
Register Definition
VID - Vendor Identification Register (0x000) on page 9-11
DID - Device Identification Register (0x002) on page 9-11
PCICMD - PCI Command Register (0x004) on page 9-11
PCISTS - PCI Status Register (0x006) on page 9-12
RID - Revision Identification Register (0x008) on page 9-13
CCODE - Class Code Register (0x009) on page 9-13
CLS - Cache Line Size Register (0x00C) on page 9-14
PLTIMER - Primary Latency Timer (0x00D) on page 9-14
HDR - Header Type Register (0x00E) on page 9-14
BIST - Built-in Self Test Register (0x00F) on page 9-14
BAR0 - Base Address Register 0 (0x010) on page 9-14
BAR1 - Base Address Register 1 (0x014) on page 9-14
PBUSN - Primary Bus Number Register (0x018) on page 9-15
SBUSN - Secondary Bus Number Register (0x019) on page 9-15
SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-15
SLTIMER - Secondary Latency Timer Register (0x01B) on page 9-15
IOBASE - I/O Base Register (0x01C) on page 9-15
IOLIMIT - I/O Limit Register (0x01D) on page 9-16
SECSTS - Secondary Status Register (0x01E) on page 9-16
MBASE - Memory Base Register (0x020) on page 9-16
MLIMIT - Memory Limit Register (0x022) on page 9-17
PMBASE - Prefetchable Memory Base Register (0x024) on page 9-
17
PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 9-17
PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 9-18
PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 9-18
IOBASEU - I/O Base Upper Register (0x030) on page 9-18
IOLIMITU - I/O Limit Upper Register (0x032) on page 9-18
CAPPTR - Capabilities Pointer Register (0x034) on page 9-19
EROMBASE - Expansion ROM Base Address Register (0x038) on
page 9-19
INTRLINE - Interrupt Line Register (0x03C) on page 9-19
INTRPIN - Interrupt PIN Register (0x03D) on page 9-19
9 - 3 February 1, 2011