Message Signaled Interrupt Capability Structure - Renesas IDT 89HPES4T4 User Manual

IDT Configuration Registers
Notes
PES4T4 User Manual
Bit Field
Type
Field Name
14:13 DSCALE
15 PMES RW1C
21:16 Reserved
22 B2B3
23 BPCCE
31:24 DATA

Message Signaled Interrupt Capability Structure

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)
Bit Field
Type
Field Name
7:0 CAPID RO
15:8 NXTPTR RWL
16 EN RW
19:17 MMC RO
22:20 MME RW
23 A64 RO
31:24 Reserved RO
MSIADDR - Message Signaled Interrupt Address (0x0D4)
Bit Field
Type
Field Name
1:0 Reserved RO
Default
Value
RO 0x0 Data Scale. The optional data register is not imple-
mented.
0x0 PME Status. This bit is set if a PME is generated by the
S FRSticky port even if the PMEE bit is cleared. This bit is not set
when the bridge is propagating a PME message but the
port is not itself generating a PME.
Since the upstream port never generates a PME, this bit
will never be set in that port.
RO 0x0 Reserved field.
RO 0x0 B2/B3 Support. Does not apply to PCI Express.
RO 0x0 Bus Power/Clock Control Enable. Does not apply to
PCI Express.
RO 0x0 Data. This optional field is not implemented.
Default
Value
0x5 Capability ID. The value of 0x5 identifies this capability as a
MSI capability structure.
0x0 Next Pointer. This field contains a pointer to the next capa-
bility structure. This field is set to 0x0 indicating that it is the
last capability.
0x0 Enable. This bit enables MSI.
0x0 - (disable) disabled
0x1 - (enable) enabled
0x0 Multiple Message Capable. This field contains the number
of requested messages.
0x0 Multiple Message Enable. Hardwired to one message.
0x1 64-bit Address Capable. The bridge is capable of generat-
ing messages using a 64-bit address.
0x0 Reserved field.
Default
Value
0x0 Reserved field.
9 - 34
Description
Description
Description
February 1, 2011