Figure 2.4 Non-Common Clock On Upstream And Downstream - Renesas IDT 89HPES4T4 User Manual

IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
Root Complex
Low
Clock Generator
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)
Initialization
A boot configuration vector consisting of the signals listed in Table 2.1 is sampled by the PES4T4 during
a fundamental reset when PERSTN is negated. The boot configuration vector defines essential parameters
for switch operation. Since the boot configuration vector is sampled only during a fundamental reset
sequence, the value of signals which make up the boot configuration vector is ignored during other times
and their state outside of a fundamental reset has no effect on the operation of the PES4T4.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more informa-
tion on the serial EEPROM.
The external serial EEPROM may be used to override the function of some of the signals in the boot
configuration vector during a fundamental reset. The signals that may be overridden are noted in Table 2.1.
The state of all of the boot configuration signals in Table 2.1 sampled during the most recent cold reset may
be determined by reading the SWSTS register.
PES4T4
Port 0
CCLKUS
PEREFCLK
Clock Generator
2 - 3
Clock Operation
Port 2
EP
Port 4 EP
CCLKDS
Low
Clock Generator *
* May be unique for each EP
February 1, 2011