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IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
Fundamental Reset
A fundamental reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin. Refer to the device datasheet for power sequencing requirements.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
When configured to operate in normal mode, the following reset sequence is executed.
1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.1. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental
reset is the result of a one being written to the SWCTL register).
Examine the state of the sampled SWMODE[2:0] signals to determine the switch operating
mode.
3. The PLL and SerDes are initialized.
4. Link training begins. While link training is in progress, proceed to step 5.
5. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.
6. If the switch operating mode is not a test mode, the reset signal to the PCI Express stacks and asso-
ciated logic is negated but they are held in a quasi-reset state in which the following actions occur.
All links enter an active link training state within 20ms of the clearing of the fundamental reset
condition.
Within 100 ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration
request retry status completion. All other transactions are ignored.
7. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate PES4T4 registers are updated.
If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link
State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using
the current link parameters.
If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in
the SMBUSSTS register.
When serial EEPROM initialization completes or when an error is detected, the DONE bit in the
SMBUSSTS register is set.
8. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master SMBus, the control/status registers, and the stacks which continue to be held in
a quasi-reset state and respond to configuration transactions with a retry. The device remains in this
state until the RSTHALT bit is cleared. In this mode, an external agent may read and write any
internal control and status registers and may access the external serial EEPROM via the EEPRO-
MINTF register.
9. Normal device operation begins.
The PCIe base specification indicates that normal operation should begin within 1.0 second after a
fundamental reset of a device. The reset sequence above guarantees that normal operation will begin
within this period as long as the serial EEPROM initialization process completes within 200 ms. Under
normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master
SMBus operating frequency of 100 KHz.
2 - 5
Clock Operation
February 1, 2011
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