Function Of Each Block; Phy Layer Control Circuit; Link Layer Control Circuit; Tsp Ic Interface - Fujitsu MB86617A Specification Sheet

LSI S pecification

3.2. Function of Each Block

This section explains the function of each block for MB86617A.
< PHY Layer Control Circuit
<
This circuit is for the Physical layer of IEEE 1394 with the following functions.
> Asynchronous transfer is supported under cable environment.
> Maximum transfer data rate : 393.216Mbit/sec.
> with three ports for transceiver/receiver : transfer IEEE1394 packet
> with bus monitor, initial performance for occurring bus reset, speed signaling, arbitration, encode/decode : transfer/receive data
< LINK Layer Control Circuit
<
This circuit generates standard packet for IEEE1394, controls transfer, and performs the following functions.
> Generates and checks 32 bit CRC for header and data of packet.
> Activates cycle master function with integrated 32 bit cycle timer register
< TSP IC Interface
<
This TSP IC Interface has two exclusive ports with the following functions for transmitting/receiving TSP IC, MPEG2-TS and DSS
data, and receiving DV data.
> Adds time stamp to both MPEG2 -TS and DSS data.
> Outputs received data just when the value of time stamp (SPH) and cycle timer is matched with each other.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
< CP IC Interface
<
This interface adds the copy information to CP IC so as to correspond to copy protect.
< Data Bridge
<
This Data Bridge packets MPEG2-TS, DSS, and DVC, and re-builds the receiving data.
At data transmission, this section adds Isochronous packet header and CIP header, and connects/separates source packet
When transmitting 2ch, it connects Isochronous packet.
At data receipt, it deletes Isochronous packet header and CIP header, restores by unit of source packet.
When receiving 2ch, it separates Isochronous packet and divide them to each FIFO.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
Rev.1.0
7
MB86617A
Fujitsu VLSI