Data Bridge Receive Information Setting Register - Fujitsu MB86617A Specification Sheet

LSI S pecification

7.19. Data Bridge Receive Information Setting Register

Data bridge receive information register performs the setting of receive packet.
Bit Bit
AD R/W
15 14
Rx Rx
3Ch R/
start end
-B -B
Initial Value '0' '0'
BIT Bit Name
15 Rx start-B
14 Rx end-B
13~8 Rx channel-B
7 Rx start-A
6 Rx end-A
5 - 0 Rx-channel-A
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
Rx channel-B
"00 h"
Action Value
Automatically clears when receive process is executed by bridge- Bch after setting
0
at '1'.
Read/
Write
1 Executes receive process by bridge -Bch.
Automatically clears when receive process is stopped by bridge -Bch after setting at
0
'1'.
Read/
Write
1 Stops receive process by bridge -Bch.
Read/ Write in Isochronous packet channel to be received by bridge-Bch.
-
Write (MSB: bit8, LSB: bit3)
Automatically clears when receive process is executed by bridge- Ach after setting
0
at '1'.
Read/
Write
1 Starts receive process by bridge -Ach.
Automatically clears when receive process is stopped by bridge -Ach after setting at
0
'1'.
Read/
Write
1 Stops receive process by bridge -Ach.
Read/ Write in Isochronous packet channel to be received by bridge-Ach
-
Write (MSB: bit5, LSB: bit0)
Bit Bit Bit Bit
9 8 7 6
Rx Rx
start end
-A -A
'0' '0'
Function
52
MB86617A
Bit Bit Bit Bit
5 4 3 2
Rx channel-A
"00 h"
Fujitsu VLSI
Bit Bit
1 0