P Hysical Register #05 ( Read / Write ) - Fujitsu MB86617A Specification Sheet

LSI S pecification
8.7. Physical register #05 (read/write)
Physical Register#05 is the register indicating availability of cable supply power standard and timeout detect of arbitration state machine.
phy/
Bit Bit
R/W
link-
15 14
addr
0A h R/W - -
Initial Value '0' '0'
< Description of Each Bit <
BIT Bit Name
15 - 8 reserved
7 Resume_Int
6 ISBR
5 Loop
4 Pwr_fail
3 Timeout
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
- - - -
'0' '0' '0' '0'
Action Value
Read - Always indicate '0'.
Write - Always write in '0'.
0 Does not indicate '1' at Port_event bit during resume processing.
Read/
Write
1 Indicates '1' at Port_event bit during resume processing.
0 Does not perform short bus reset.
Read/
Write
Performs short bus reset. Automatically clears to '0' at the completion of bus
1
reset.
0 Indicates that port connection is in a loop.
Read
1 Indicates that port connection is in a loop.
Write - Clears the bit value to '0' by writing in '1'.
0 Indicates that the cable supply power satisfies the standard.
Read
1 Indicates that the cable supply power does not satisfy the standard.
Write - Clears the bit value to '0' by writing in '1'.
0 Indicates that timeout is not detected by arbitration state machine.
Read
1 Indicates that timeout is det ected by arbitration state machine.
Write - Clears the bit value to '0' by writing in '1'.
Bit Bit Bit Bit
9 8 7 6
R e s u m e
- - ISBR
_ I n t
'0' '0' '0'' '0'
Function
88
MB86617A
Bit Bit Bit Bit
5 4 3 2
Pwr Time Port_
Loop
_fail out event
'0' '0' '0' '0'
Fujitsu VLSI
Bit Bit
1 0
Enab E n a b _
_accel multi
'0' '0'