Fujitsu MB86617A Specification Sheet page 116

LSI S pecification
Interrupt
INT23 Cycle start packet received
INT24 Cycle start packet send
INT25 Physical packet send
INT26 Extended PHY packet received
Physical configuration packet
INT27
received
INT28 Link on packet received
INT29 Self-ID packet received
INT30 Receive late occurred
INT31 Instruction abort (State)
INT32 Transmit late occurred
Rev.1.0
Interrupt Item
Received cycle start packet normally when self node is not root
> Isochronous cycle starts.
Completed to send Cycle start packet when self node is root.
Completed to send Physical packet.
Received Extended PHY packet normally.
Received Physical configuration packet normally.
> Reflect to Physical register#01(address Phy/Link-reg 02h) and switch
Received Link-on packet addressed to self-node normally.
> Assert LINKON terminal output simultaneously.
Received Self -ID packet normally.
Receive-late was occured.
Though Instruction was issued, it was not accepted bec ause the content
was not appropriate for this device.
e.g.) >Issued " Remove sleep" (02h) instruction in spite of not in sleep
Transmit-late was occured.
>Delete packet transmitted.
Description
Set ISO cycle Bit (Bit12) of flag & status register (address 02h) at '1'
simaltaneously with this interrupt report.
to specified performance automatically.
Store data at ASYNC receive specific buffer.
Delete packet received.
condition.
>Issued "Instruction suspend"(62h) instruction without instruction
to be stopped.
>Used undefine operand against issued instruction.
>Issued instruction was undefined.
etc.
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MB86617A
Fujitsu VLSI