R Egister [B] - Fujitsu MB86617A Specification Sheet

LSI S pecification
7.13. Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header
Setting Register [B]
Receiv e DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge-Bch.
Transmit DSS packet header setting register [B] sets DSS packet header range of DSS packet received by bridge-Bch.
Bit Bit
AD R/W
15 14
Rx-SI
R
F-B
28h
Tx-SIF
W
-B
R
2Ah
W
R
2Ch
W
R
2Eh
W
R
30h
W
Initial Value
BIT Bit Name
Rx-SIF-B
15 (28h)
T x-SIF-B
Rx-System
clock count-B
14 - 0 (28h)
15 - 8(2Ah)
T x-System
clock count-B
Rx-EF-B
7(2Ah)
Tx-EF-B
6 - 0 (2Ah)
7 - 0 (2Ch)
reserved
15 - 0 (2Eh)
15 - 0 (30h)
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
Rx-maximum bit rate-B (low)
T x-maximum bit rate-B (low)
Action Value
Read - Indicates SIF range of receive DSS packet header.
Write - Write in SIF range of transmit DSS packet header.
Indicate System clock count range of receive DSS packet header.
Read -
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Write in System clock count range of transmit DSS packet header.
Write -
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Read - Indicates EF range of received DSS packet header.
Write - Write in EF range of transmit DSS packet header.
Read - Indicates reserved range of receive DSS packet header.
Write - Write in reserved range of transmit DSS packet header.
Bit Bit Bit Bit
9 8 7 6
Rx-System clock count-B (high)
T x-System clock count-B (high)
Rx-E
F-B
Tx-E
F-B
reserved
reserved
reserved
reserved
reserved
reserved
"0000 h "
Function
45
MB86617A
Bit Bit Bit Bit
5 4 3 2
reserved
reserved
Fujitsu VLSI
Bit Bit
1 0