Fujitsu MB86617A Specification Sheet page 122

Ieee1394 serial bus controller for dtv
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LSI S pecification
< Flow chart after bus reset completion
<
Issue Asynchronous receive (03h)
Read one word from receive
Asynchronous data port.
'1'
Issue Remove busy (04h) instruction.
Figure 11.2.1.2 Flow example for Self-ID packet receiving after bus reset completed
Note1: When Asyn- FIFO sel (mode-control register[3]) is 1 and send/rec (mode-control register [2]) is 1, Asynchronous receive
FIFO (256 byte) and Bridge FIFO (2048 byte) are used with combined as Asynchronous receive buffer.
In other case, Asynchronous receive FIFO (256 byte) and Asynchronous transmit FIFO (256 byte) are used with
combined.
Note2: When Asyn- FIFO sel is 1 and transmit/rec is 1, Asynchronous transmitting FIFO (256 byte) and Bridge FIFO (2048 byt)
are cleared,
When Asyn-FIFO SEL is 1 and transmit/rec is 0, Asynchronous receiving FIFO (256 byte) and Asynchronous
transmitting FIFO (256 byte) are cleared. Asynchronous transmit FIFO and Bridge FIFO are combined to be set in
Asynchronous transmit buffer. Set Asynchronous receive FIFO to Asynchronous receive buffer.
When Asyn- FIFO sel is 0, Asynchronous receive FIFO (256 byte) and Asynchronous transmit FIFO (256 byte) are cleared
and re-set Asynchronous receive FIFO to Asynchronous receive buffer, Asynchronous transmit FIFO to Asynchronous
transmit buffer.
Rev.1.0
<Host>
START
Read Self -ID?
No
Yes
instruction.
data req bit
'0'
<Device>
Prepare for reading received data.
Read one word of the received data
and increment the read pointer of
Receive Remove busy(04h) instruction.
recv busy bit=0
Clear the receive Asynchronous buffer
and set FIFO according to FIFO mode.
117
MB86617A
buffer.
(Note 2)
END
Fujitsu VLSI

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