Chapter 6 Internal Register - Fujitsu MB86617A Specification Sheet

LSI S pecification

Chapter 6 Internal Register

This chapter explains the MB86617A internal register.
Note that the access of internal register is applied only 16 bits access.
Address
(HEX)
00
02
04
06
08
0A
0C
0E
10 TSP transmit information setting [A]
12 TSP transmit information setting [B]
14 transmit offset setting [A] (upper)
16 transmit offset setting [A] (lower)
18 transmit offset setting [B] (upper)
1A transmit offset setting [B] (lower)
1C TSP receive information setting
transmit DSS packet header setting [A]
1E
Rev.1.0
WRITE
Register Name
mode-control
(reserved)
Instruction-fetch
Interrupt-mask setting [A]
Interrupt-mask setting [B]
(reserved)
A-buffer data port transmit
(reserved)
(most significant)
Interrupt indicate [A]
Interrupt indicate [B]
Receive Acknowledge
A-buffer data port receive
TSP transmit information setting [A]
TSP transmit information setting [B]
transmit offset setting [A] (upper)
transmit offset setting [A] (lower)
transmit offset setting [B] (upper)
transmit offset setting [B] (lower)
TSP receive information setting
receive DSS packet header setting [A]
19
MB86617A
READ
Register Name
mode-control
flag & status
Instruction-fetch
(reserved)
(most significant)
Fujitsu VLSI