Fujitsu MB86617A Specification Sheet page 20

LSI S pecification
IERRA
IERRB
DSSCLKA
DSSCLKB
Rev.1.0
Output pin for noticing error of receive data (on port A)
O
'H' active signal
Output pin for noticing error of receive data (on port B)
O
'H' active signal
I Clock input pin for DSS data (27MHz)
Clock input pin for DSS data (27MHz)
I
15
MB86617A
Fujitsu VLSI