Late Packet Decision Range Setting Register [A - Fujitsu MB86617A Specification Sheet

LSI S pecification

7.21. Late Packet Decision Range Setting Register [A]

Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge -Ach.
Bit Bit
AD R/W
15 14
40h R/W
Initial Value
BIT Bit Name
15 - 8
late range-A
7 - 0
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-Transmit:
Packet is transmitted normally when calculation result of "SPH" minus "CTR" for source packet transmitted from Bridhe-Ach is within the
"late range-A + '0000'h".
If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[A] (14h to 16h).
-Receive:
Received packet is output at the point of "SPH = CTR " when calculation result of " SPH" minus " CTR" for source packet received at
Bridhe -Ach is within the "late range-A + '0000'h" (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
Action Value
Write in Late packet decision range.
Setting range is 0h to FFh (unit: 125 S).
Read/
-
Write
Write in Late packet decision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
Bit Bit Bit Bit
9 8 7 6
late range-A
"0000 h "
Function
55
MB86617A
Bit Bit Bit Bit
5 4 3 2
Fujitsu VLSI
Bit Bit
1 0