Fujitsu MB86617A Specification Sheet page 33

Ieee1394 serial bus controller for dtv
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LSI S pecification
BIT
Bit Name
Asyn-FIFO
3
sel
2
send/rec
1
TSP stand-by
0
CP stand-by
Note 1) Refer to "Self-ID Packet Receive Operation" for the internal operation flow and read-out flow of with this bit set at '1'.
Rev.1.0
Action
value
0
Uses 2K byte FIFO on LINK I/F side of bridge for Isochronous transmit/receive.
Read/
Write
1
Uses 2K byte FIFO on LINK I/F side of bridge for Asynchronous transmit/receive.
0
Uses 2K byte FIFO for Asynchronous transmit with Asyn-FIFO sel (bit3) '1'.
Read/
Write
1
Uses 2K byte FIFO for Asynchronous receive with Asyn-FIFO sel (bit3) '1'.
0
Activates TSP -IC I/F terminal output.
Read/
Write
1
Disables TSP-IC I/F terminal output, and brings it in high impedance status.
0
Activates CP I/F terminal output.
Read/
Write
0
Disables CP I/F terminal output, and brings it in high impedance status.
Function
28
MB86617A
Fujitsu VLSI

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