Fujitsu MB86617A Specification Sheet page 26

LSI S pecification
Address
(HEX)
50
52
54
56
58
5A
5C
5E
60 PHY/LINK register address setting
62 PHY/LINK register access port
64
66
68
6A
6C
6E
70
72
74
76
78
7A
7C
7E
Rev.1.0
WRITE
Register Name
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
data bridge transmit/receive status [B]
Isochronous channel monitor 1
Isochronous channel monitor 2
Isochronous channel monitor 3
Isochronous channel monitor 4
cycle-time-monitor (upper)
cycle-time-monitor (lower)
Ping time monitor
PHY/LINK register address setting
PHY/LINK register access port
Revision indicate register (upper)
Revision indicate register (lower)
21
MB86617A
READ
Register Name
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
Fujitsu VLSI