Isochronous Interface - Fujitsu MB86617A Specification Sheet

Ieee1394 serial bus controller for dtv
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LSI S pecification

5.2. Isochronous Interface

This section explains the pin function of Isochronous interface.
Signal Name
TSVALIDA
TSSYNCA
TSCLKA
TSDA7 - 0
TSCGMSA
SELIOA
SELTSPA
TSVALIDB
TSSYNCB
TSCLKB
TSDB7 - 0
TSCGMSB
SELIOB
SELTSPB
ICLK
XILWRE
XIV
XFP
Rev.1.0
I/O
I.O pin for indicating effective data period of TS packet (on port A)
I/O
'H' active signal
Input/Output pin for indicating leading data of TS packet (on port A)
I/O
'H' active signal
On transmitting: sync clock input pin for input data of TS packet
I/O
On receiving
: sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
I/O
I/O pin for TS packet data (on Port A)
Serial input pin for CGMS and TSCH information (on port A)
I
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port A
O
Outputs 'L' at transmitting and 'H'at receiving
O
Output pin for switching output device from port A
I.O pin for indicating effective data period of TS packet (on port B)
I/O
'H' active signal
Input/Output pin for indicating leading data of TS packet (on port B)
I/O
'H' active signal
On transmitting: sync clock input pin for input data of TS packet
I/O
On receiving
: sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
I/O
I/O pin for TS packet data (on port B)
Serial input pin for CGMS and TSCH information (on port B)
I
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port B
O
Outputs 'L' at transmitting and 'H'at receiving
O
Output pin for switching output device from port B
I
Clock input pin from DV-IC
Output pin for signal to be allowed accessing to Isochronous-FIFO
O
Asserted by completing reception of data for one source packet
'L' active signal
Input signal for enable signal of Isochronous data
I
Output Isochronous- FIFO data to data output pin while this signal in active.
Switch data synchronizing with rise edge of ICLK
Output pin of time stamp trigger signal
O
'L' active signal
14
MB86617A
Function
Fujitsu VLSI

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