Fujitsu MB86617A Specification Sheet page 5

LSI Specification
9.2. D E
ESCRIPTION OF ACH
CHAPTER 10 INTERRUPT ..................................................................................................................................................................... 106
10.1. I -
NTERRUPT FACTOR
.......................................................................................................................................................................................... 108
10.2. I
NTERRUPT
10.3. D I
ESCRIPTION OF NTERRUPT
CHAPTER 11 OPERATION ...................................................................................................................................................................112
11.1. I ................................................................................................................................................................................ 113
NITIALIZATION
11.2. S -ID P R
ELF ACKET ECEIVING
11.2.1 Self -ID Packet Receive at Bus Reset Process .............................................................................................................115
11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping................................................................................ 118
11.3. A P
SYNCHRONOUS ACKET
11.4. A P
SYNCHRONOUS ACKET
11.5. I P
SOCHRONOUS ACKET
11.6. I P
SOCHRONOUS ACKET
CHAPTER 12 SYSTEM CONFIGURATION ...................................................................................................................................130
12.1. R C
ECOMMENDED ONNECTION FOR
12.2. R C
ECOMMENDED ONNECTION FOR
12.3. R C
ECOMMENDED ONNECTION FOR
12.4. C
ONFIGURATION OF
Rev.1.0
............................................................................................................................................... 103
I
NSTRUCTION
I R &
NDICATOR EGISTER INTERRUPT
............................................................................................................................................................ 109
.........................................................................................................................................................114
T ................................................................................................................................. 120
RANSMITTING
R .........................................................................................................................................122
ECEIVING
T ..................................................................................................................................... 125
RANSMITTING
R .............................................................................................................................................128
ECEIVING
1934 P
ORT
C P
ABLE OWER
B - PLL L
UILD IN
F C C
EEDBACK IRCUIT AT RYSTAL
- S R
MASK ETTING EGISTER
( ) .......................................................................................... 131
FOR ONE PORT
S ..................................................................................................132
UPPLY
F .........................................................................................133
OOP ILTER
O ...................................................................................134
SCILLATOR
v
MB86617A
.............................................................107
Fujitsu VLSI