Transmit Packet Link/Split Setting Register - Fujitsu MB86617A Specification Sheet

Ieee1394 serial bus controller for dtv
Table of Contents

Advertisement

LSI S pecification

7.20. Transmit Packet Link/Split Setting Register

Transmit packet link/split setting register is the register that sets number of link and split of source packets to be transmitted.
Bit
Bit
AD
R/W
15
14
o/e
Tx
3Eh
R/W
select-
o/e-B
B
Initial Value
'0'
'0'
BIT
Bit Name
15
o/e select-B
14
Tx o/e-B
13
NF5SPB
12 - 10
SPQB
9 - 8
DBQB
7
o/e select-A
6
Tx o/e-A
Rev.1.0
Bit
Bit
Bit
Bit
13
12
11
10
NF5
SPQB
SPB
'0'
"000 b"
Action
Value
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
0
packet header to be transmitted by bridge -Bch.
Read/
Write
Selects Tx o/e- B (bit14) setting value as odd/even range of Isochronous packet
1
header to be transmitted by bridge -Bch
Write in odd/even range of transmit Isochronous packet header.
Read/
-
Valid with o/e select- B (bit15) setting value '1', and reads in this setting value to
Write
transmit Isochronous packet header.
Executes 2SP combined transmission as FIFO NFULL operation when setting of
0
2SP separated transmission or combined transmission for less than 2SP.
Read/
With more than 3 SP, executes according to setting.
Write
1
Executes 5 SP combined transmission at FIFO FULL.
Read/
-
Write in number of link of source packet processed by bridge-Bch.
Write
Read/
-
Write in number of split of source packet processed by bridge-Bch.
Write
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
0
packet header to be transmitted by bridge -Bch.
Read/
Write
Selects Tx o/e-B b (bit6) setting value as odd/even range of Isochronous packet
1
header to be transmitted by bridge-Bch
Write in odd/even range of transmit Isochronous packet header.
Read/
-
Valid with o/e select-B (bit7) setting value '1', and reads in this setting value to
Write
transmit Isochronous packet header.
Bit
Bit
Bit
Bit
9
8
7
6
o/e
Tx
DBQB
select-
o/e-A
A
"00 b"
'0'
'0'
Function
53
MB86617A
Bit
Bit
Bit
Bit
5
4
3
2
NF5
SPQA
SPA
'0'
"000 b"
Fujitsu VLSI
Bit
Bit
1
0
DBQA
"00 b"

Advertisement

Table of Contents
loading

Table of Contents