Altera Cyclone V Reference Manual page 41

Chapter 2: Board Components
Components and Interfaces
Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board
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August 2017 Altera Corporation
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Cyclone V GT
Schematic Signal Name
Pin Number
HSMB_RX_P3
HSMB_TX_N3
HSMB_RX_N3
HSMB_TX_P2
HSMB_RX_P2
HSMB_TX_N2
HSMB_RX_N2
HSMB_TX_P1
HSMB_RX_P1
HSMB_TX_N1
HSMB_RX_N1
HSMB_TX_P0
HSMB_RX_P0
HSMB_TX_N0
HSMB_RX_N0
HSMB_SDA
HSMB_SCL
JTAG_TCK
HSMB_JTAG_TMS
HSMB_JTAG_TDO
HSMB_JTAG_TDI
HSMB_CLK_OUT0
HSMB_CLK_IN0
HSMB_WEn
HSMB_RASn
HSMB_ADDR_CMD0
HSMB_CASn
HSMB_DQ0
HSMB_DQ1
HSMB_DQ2
HSMB_DQ3
HSMB_DQ4
HSMB_DQ5
HSMB_DQ6
HSMB_DQ7
HSMB_DQ8
HSMB_DQ9
HSMB_DQ10
HSMB_DQ11
I/O Standard
G2 1.5-V PCML Transceiver RX bit 3
F3 1.5-V PCML Transceiver TX bit 3n
G1 1.5-V PCML Transceiver RX bit 3n
H4 1.5-V PCML Transceiver TX bit 2
J2 1.5-V PCML Transceiver RX bit 2
H3 1.5-V PCML Transceiver TX bit 2n
J1 1.5-V PCML Transceiver RX bit 2n
K4 1.5-V PCML Transceiver TX bit 1
L2 1.5-V PCML Transceiver RX bit 1
K3 1.5-V PCML Transceiver TX bit 1n
L1 1.5-V PCML Transceiver RX bit 1n
M4 1.5-V PCML Transceiver TX bit 0
N2 1.5-V PCML Transceiver RX bit 0
M3 1.5-V PCML Transceiver TX bit 0n
N1 1.5-V PCML Transceiver RX bit 0n
L20 2.5-V CMOS Management serial data
E27 2.5-V CMOS Management serial clock
AK5 2.5-V CMOS JTAG clock signal
— 2.5-V CMOS JTAG mode select signal
— 2.5-V CMOS JTAG data output
— 2.5-V CMOS JTAG data input
D25 2.5-V CMOS Dedicated CMOS clock out
A22 2.5-V CMOS Dedicated CMOS clock in
B24 2.5-V CMOS Write enable
A23 2.5-V CMOS Row address select
L18 2.5-V CMOS Memory address or command
C21 2.5-V CMOS Column address select
E22 2.5-V CMOS Memory data bus
G20 2.5-V CMOS Memory data bus
F20 2.5-V CMOS Memory data bus
D24 2.5-V CMOS Memory data bus
C26 2.5-V CMOS Memory data bus
G21 2.5-V CMOS Memory data bus
F21 2.5-V CMOS Memory data bus
D27 2.5-V CMOS Memory data bus
F23 2.5-V CMOS Memory data bus
C29 2.5-V CMOS Memory data bus
E24 2.5-V CMOS Memory data bus
H21 2.5-V CMOS Memory data bus
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Description
Cyclone V GT FPGA Development Board
Reference Manual