Altera Cyclone V Reference Manual page 36

2–28
Table 2–21. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board
Reference (U11)
76
74
73
58
69
68
25
24
28
2
95
92
93
91
94
11
12
14
16
9
55
29
31
33
34
39
41
42
43
Cyclone V GT FPGA Development Board
Reference Manual
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Schematic Signal Name
ENET_LED_LINK10
ENET_LED_LINK100
ENET_LED_LINK1000
ENET_LED_RX
ENET_LED_RX
ENET_LED_TX
ENET_MDC
ENET_MDIO
ENET_RESETN
ENET_RX_CLK
ENET_RX_D0
ENET_RX_D1
ENET_RX_D2
ENET_RX_D3
ENET_RX_DV
ENET_TX_D0
ENET_TX_D1
ENET_TX_D2
ENET_TX_D3
ENET_TX_EN
ENET_XTAL_25MHZ
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
Cyclone V GT
I/O Standard
Pin Number
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
AM8 2.5-V CMOS
AG14 2.5-V CMOS
AN9 2.5-V CMOS
AM10 2.5-V CMOS
AK14 2.5-V CMOS
AL10 2.5-V CMOS
AJ14 2.5-V CMOS
AK12 2.5-V CMOS
AH14 2.5-V CMOS
AB14 2.5-V CMOS
AD15 2.5-V CMOS
AB15 2.5-V CMOS
AB13 2.5-V CMOS
AC14 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
Chapter 2: Board Components
Components and Interfaces
Description
10-Mb link LED
100-Mb link LED
1000-Mb link LED
RX data active LED
RX data active LED
TX data active LED
Management bus data clock
Management bus data
Device reset
RGMII receive clock
RGMII receive data bus
RGMII receive data bus
RGMII receive data bus
RGMII receive data bus
RGMII receive data valid
RGMII transmit data bus
RGMII transmit data bus
RGMII transmit data bus
RGMII transmit data bus
RGMII transmit enable
25-MHz RGMII transmit clock
Media dependent interface
Media dependent interface
Media dependent interface
Media dependent interface
Media dependent interface
Media dependent interface
Media dependent interface
Media dependent interface
August 2017 Altera Corporation