Altera Cyclone V Reference Manual page 50

2–42
Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board Reference
N7
T3
M2
N8
M3
K3
K9
J7
K7
L2
E7
E3
F7
F2
F8
H3
H8
G2
H7
F3
G3
K1
J3
T2
L3
L8
Cyclone V GT FPGA Development Board
Reference Manual
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Schematic Cyclone V GT
Signal Name Pin Number
AM13
DDR3A_A12
AN13
DDR3A_A13
AN16
DDR3A_BA0
AN17
DDR3A_BA1
AP17
DDR3A_BA2
AP15
DDR3A_CASN
AP26
DDR3A_CKE
AA18
DDR3A_CLK_P
AA17
DDR3A_CLK_N
AA16
DDR3A_CSN
AL30
DDR3A_DM4
AH23
DDR3A_DQ32
AG23
DDR3A_DQ33
AN32
DDR3A_DQ34
AN29
DDR3A_DQ35
AK25
DDR3A_DQ36
AJ25
DDR3A_DQ37
AK28
DDR3A_DQ38
AM30
DDR3A_DQ39
AC21
DDR3A_DQS_P4
AD21
DDR3A_DQS_N4
AN21
DDR3A_ODT
AP14
DDR3A_RASN
AJ22
DDR3A_RESETN
AN12
DDR3A_WEN
DDR3A_ZQ03
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
Chapter 2: Board Components
Memory
Description
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data strobe P byte lane 4
Data strobe N byte lane 4
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
August 2017 Altera Corporation