Altera Cyclone V Reference Manual page 53

Chapter 2: Board Components
Memory
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6)
Board Reference
N7
T3
M2
N8
M3
K3
K9
J7
K7
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
K1
J3
August 2017 Altera Corporation
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Schematic Cyclone V GT
Signal Name Pin Number
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
AF32
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
AC34
DDR3B_DM2
W34
DDR3B_DM3
AD34
DDR3B_DQ16
AC33
DDR3B_DQ17
AG34
DDR3B_DQ18
AB33
DDR3B_DQ19
AE33
DDR3B_DQ20
DDR3B_DQ21
AH34
DDR3B_DQ22
W32
DDR3B_DQ23
DDR3B_DQ24
DDR3B_DQ25
DDR3B_DQ26
AA33
DDR3B_DQ27
DDR3B_DQ28
DDR3B_DQ29
DDR3B_DQ30
DDR3B_DQ31
DDR3B_DQS_P2
DDR3B_DQS_N2
DDR3B_DQS_P3
DDR3B_DQS_N3
AA32
DDR3B_ODT
DDR3B_RASN
I/O Standard
T31 1.5-V SSTL Class I
T30 1.5-V SSTL Class I
J31 1.5-V SSTL Class I
N29 1.5-V SSTL Class I
P27 1.5-V SSTL Class I
N27 1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
R30
Class I
Differential 1.5-V SSTL
R29
Class I
V27 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
V32 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
U29 1.5-V SSTL Class I
V34 1.5-V SSTL Class I
U34 1.5-V SSTL Class I
1.5-V SSTL Class I
R34 1.5-V SSTL Class I
Y33 1.5-V SSTL Class I
P34 1.5-V SSTL Class I
U28 1.5-V SSTL Class I
Differential 1.5-V SSTL
V24
Class I
Differential 1.5-V SSTL
V23
Class I
Differential 1.5-V SSTL
U24
Class I
Differential 1.5-V SSTL
U25
Class I
1.5-V SSTL Class I
Y32 1.5-V SSTL Class I
2–45
Description
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data strobe P byte lane 2
Data strobe N byte lane 2
Data strobe P byte lane 3
Data strobe N byte lane 3
On-die termination enable
Row address select
Cyclone V GT FPGA Development Board
Reference Manual