Altera Cyclone V Reference Manual page 17

Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)
Board
Reference (U32)
L16
L11
L15
L12
M16
L13
M15
L14
N16
M13
N15
K5
K1
D3
C2
C3
E3
D2
E4
D1
E5
F3
E1
F4
F2
F1
F6
G2
G3
N3
J3
B10
B3
C10
C12
C6
N1
J4
H1
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Schematic Signal Name I/O Standard
FM_D6
FM_D7
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
FORCE_FAN
FPGA_CEN
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
FPGA_CVP_CONFDONE
FPGA_DCLK
FPGA_MSEL0
FPGA_MSEL1
FPGA_MSEL2
FPGA_MSEL3
FPGA_MSEL4
FPGA_NCONFIG
FPGA_NSTATUS
FPGA_PR_DONE
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V FM data bus
1.8-V DIP switch to enable or disable the fan
2.5-V FPGA chip enable
2.5-V FPGA configuration done LED
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration data
2.5-V FPGA configuration via protocol done LED
2.5-V FPGA configuration clock
2.5-V FPGA mode select 0
2.5-V FPGA mode select 1
2.5-V FPGA mode select 2
2.5-V FPGA mode select 3
2.5-V FPGA mode select 4
2.5-V FPGA configuration active
2.5-V FPGA configuration ready
2.5-V FPGA partial reconfiguration done
Description
Cyclone V GT FPGA Development Board
Reference Manual
2–9