Altera Cyclone V Reference Manual page 11

Chapter 2: Board Components
Board Overview
Table 2–1. Board Components (Part 2 of 4)
Board Reference
J5
SW4
SW5
S6
S5
D7
D6
D5
D21
D12, D13, D14
D22, D23, D24,
D25, D26
D32
D3, D4, D19, D20 HSMC port LEDs
D1, D2
D34, D35, D44,
D45
Clock Circuitry
X6
X2
X3
X4
X5
J11, J12
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Type
Mini USB type-AB connector
Board settings DIP switch
FPGA configuration mode DIP
Switch
Program select push button
Program configuration push
button
Configuration done LED
Load LED
Error LED
Power LED
Program select LEDs
Ethernet LEDs
SDI LEDs
HSMC port present LED
PCI Express link LEDs
50-MHz oscillator
100-MHz oscillator
148.500-MHz oscillator
100-MHz oscillator
125-MHz oscillator
SDI transceiver connectors
Description
USB interface for FPGA programming and debugging through the
embedded USB-Blaster II JTAG via a mini-USB type-B cable.
Controls the MAX V CPLD 5M2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
Controls the supported FPGA configuration mode by altering the MSEL
input pins. This switch can also control the fan speed by forcing it to
run at full speed, over-riding the fan control block in the MAX V CPLD.
Toggles the program select LEDs, which selects the program image
that loads from flash memory to the FPGA.
Load image from flash memory to the FGPA based on the settings of
the program select LEDs.
Illuminates when the FPGA is configured.
Illuminates when the MAX V CPLD 5M2210 System Controller is
actively configuring the FPGA.
Illuminates when the FPGA configuration from flash memory fails.
Illuminates when 5.0-V power is present.
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when you press the program select
push button. Refer to Table 2–6
Illuminates to show the connection speed as well as transmit or
receive activity.
Illuminates to show the transmit or receive activity.
You can configure these LEDs to indicate transmit or receive activity.
Illuminates when a daughtercard is plugged into the HSMC port.
You can configure these LEDs to indicate the PCI Express link width
(x1, x4) and Gen1 link.
50.000-MHz crystal oscillator for general purpose logic. This oscillator
is the input source to a clock buffer with two outputs. One output clock
goes to the FPGA and one goes to the MAX V CPLD 5M2210 System
Controller.
100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System
Controller.
148.500-MHz voltage controlled oscillator for the serial digital
interface (SDI) video. This oscillator is programmable to any frequency
between 20–810 MHz using the clock control GUI running on the
MAX V CPLD 5M2210 System Controller.
Programmable oscillator (10–810 MHz) with a default frequency of
100.000 MHz. This clock is the clock input source to a 6-output clock
buffer (U3). The buffer can select between this clock source or a pair of
SMA connectors as the input clock source.
125.000-MHz voltage controlled oscillator for the FPGA.
Drives serial data input/output to or from the SDI video port.
for the LED settings.
Cyclone V GT FPGA Development Board
Reference Manual
2–3