Altera Cyclone V Reference Manual page 52

2–44
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 6)
Board Reference
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
K1
J3
T2
L3
L8
DDR3 x16 (U22)
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
Cyclone V GT FPGA Development Board
Reference Manual
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Schematic Cyclone V GT
Signal Name Pin Number
AC31
DDR3B_DQ3
AH32
DDR3B_DQ4
DDR3B_DQ5
AN34
DDR3B_DQ6
DDR3B_DQ7
AD32
DDR3B_DQ8
AH33
DDR3B_DQ9
AB31
DDR3B_DQ10
AJ34
DDR3B_DQ11
AA31
DDR3B_DQ12
AK34
DDR3B_DQ13
W31
DDR3B_DQ14
AG33
DDR3B_DQ15
DDR3B_DQS_P0
DDR3B_DQS_N0
W29
DDR3B_DQS_P1
W30
DDR3B_DQS_N1
AA32
DDR3B_ODT
DDR3B_RASN
AG31
DDR3B_RESETN
AM34
DDR3B_WEN
DDR3B_ZQ01
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
AE34
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
Y28 1.5-V SSTL Class I
1.5-V SSTL Class I
Y27 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Y29
Class I
Differential 1.5-V SSTL
Y30
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
Y32 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
H29 1.5-V SSTL Class I
K28 1.5-V SSTL Class I
K34 1.5-V SSTL Class I
L32 1.5-V SSTL Class I
R32 1.5-V SSTL Class I
R33 1.5-V SSTL Class I
N32 1.5-V SSTL Class I
G33 1.5-V SSTL Class I
1.5-V SSTL Class I
L27 1.5-V SSTL Class I
V33 1.5-V SSTL Class I
U33 1.5-V SSTL Class I
Chapter 2: Board Components
Memory
Description
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data strobe P byte lane 0
Data strobe N byte lane 0
Data strobe P byte lane 1
Data strobe N byte lane 1
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
August 2017 Altera Corporation