Altera Cyclone V Reference Manual page 55

Chapter 2: Board Components
Memory
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 6)
Board Reference
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
K1
J3
T2
L3
L8
DDR3 x16 (U15)
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
K3
August 2017 Altera Corporation
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Schematic Cyclone V GT
Signal Name Pin Number
DDR3B_DQ41
DDR3B_DQ42
DDR3B_DQ43
DDR3B_DQ44
DDR3B_DQ45
DDR3B_DQ46
DDR3B_DQ47
DDR3B_DQS_P4
DDR3B_DQS_N4
DDR3B_DQS_P5
DDR3B_DQS_N5
AA32
DDR3B_ODT
DDR3B_RASN
AG31
DDR3B_RESETN
AM34
DDR3B_WEN
DDR3B_ZQ03
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
AE34
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
I/O Standard
N31 1.5-V SSTL Class I
G34 1.5-V SSTL Class I
R28 1.5-V SSTL Class I
H33 1.5-V SSTL Class I
P32 1.5-V SSTL Class I
H34 1.5-V SSTL Class I
R27 1.5-V SSTL Class I
Differential 1.5-V SSTL
U23
Class I
Differential 1.5-V SSTL
T23
Class I
Differential 1.5-V SSTL
T25
Class I
Differential 1.5-V SSTL
R25
Class I
1.5-V SSTL Class I
Y32 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
H29 1.5-V SSTL Class I
K28 1.5-V SSTL Class I
K34 1.5-V SSTL Class I
L32 1.5-V SSTL Class I
R32 1.5-V SSTL Class I
R33 1.5-V SSTL Class I
N32 1.5-V SSTL Class I
G33 1.5-V SSTL Class I
1.5-V SSTL Class I
L27 1.5-V SSTL Class I
V33 1.5-V SSTL Class I
U33 1.5-V SSTL Class I
T31 1.5-V SSTL Class I
T30 1.5-V SSTL Class I
J31 1.5-V SSTL Class I
N29 1.5-V SSTL Class I
P27 1.5-V SSTL Class I
N27 1.5-V SSTL Class I
2–47
Description
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data strobe P byte lane 4
Data strobe N byte lane 4
Data strobe P byte lane 5
Data strobe N byte lane 5
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Cyclone V GT FPGA Development Board
Reference Manual