Altera Cyclone V Reference Manual page 56

2–48
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)
Board Reference
K9
J7
K7
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
K1
J3
T2
L3
L8
Cyclone V GT FPGA Development Board
Reference Manual
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Schematic Cyclone V GT
Signal Name Pin Number
AF32
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
DDR3B_DM6
DDR3B_DM7
DDR3B_DQ48
DDR3B_DQ49
DDR3B_DQ50
DDR3B_DQ51
DDR3B_DQ52
DDR3B_DQ53
M31
DDR3B_DQ54
DDR3B_DQ55
DDR3B_DQ56
DDR3B_DQ57
DDR3B_DQ58
M30
DDR3B_DQ59
DDR3B_DQ60
M29
DDR3B_DQ61
DDR3B_DQ62
DDR3B_DQ63
DDR3B_DQS_P6
DDR3B_DQS_N6
DDR3B_DQS_P7
DDR3B_DQS_N7
AA32
DDR3B_ODT
DDR3B_RASN
AG31
DDR3B_RESETN
AM34
DDR3B_WEN
DDR3B_ZQ03
I/O Standard
1.5-V SSTL Class I
Differential 1.5-V SSTL
R30
Class I
Differential 1.5-V SSTL
R29
Class I
V27 1.5-V SSTL Class I
L31 1.5-V SSTL Class I
H28 1.5-V SSTL Class I
N28 1.5-V SSTL Class I
L30 1.5-V SSTL Class I
P30 1.5-V SSTL Class I
K30 1.5-V SSTL Class I
J32 1.5-V SSTL Class I
H32 1.5-V SSTL Class I
1.5-V SSTL Class I
H31 1.5-V SSTL Class I
G30 1.5-V SSTL Class I
K29 1.5-V SSTL Class I
G31 1.5-V SSTL Class I
1.5-V SSTL Class I
J30 1.5-V SSTL Class I
1.5-V SSTL Class I
J29 1.5-V SSTL Class I
L28 1.5-V SSTL Class I
Differential 1.5-V SSTL
R23
Class I
Differential 1.5-V SSTL
R24
Class I
Differential 1.5-V SSTL
P24
Class I
Differential 1.5-V SSTL
P25
Class I
1.5-V SSTL Class I
Y32 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
Chapter 2: Board Components
Memory
Description
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data bus byte lane 7
Data strobe P byte lane 6
Data strobe N byte lane 6
Data strobe P byte lane 7
Data strobe N byte lane 7
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
August 2017 Altera Corporation