Altera Cyclone V Reference Manual page 20

2–12
Cyclone V GT FPGA Development Board
Reference Manual
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The embedded USB-Blaster II in the MAX II CPLD EPM570GT100C3N normally
masters the JTAG chain. Figure 2–3
Figure 2–3. JTAG Chain
Disable
GPIO
TCK
GPIO
TMS
GPIO
Embedded
TDO
USB-Blaster II
GPIO
TDI
GPIO
JTAG Master
Enable
DIP Switch
Enable
DIP Switch
The JTAG chain control DIP switch (SW3) controls the device connection. To connect a
device or interface in the chain, their corresponding switch must be in the OFF
position. Slide all the switches to the ON position to only have the FPGA and MAX V
CPLD 5M2210 System Controller in the chain.
A Cypress EZ-USB CY7C68013A device in a 56-pin VBGA package device is used to
interface to a single type-B mini-USB connector. This device has an on-board 8051
CPU used in conjunction with embedded MAC logic to translate USB data into other
formats for use by the FPGA. This CPU uses internal RAM and a small external serial
boot ROM.
illustrates the JTAG chain.
10-pin
JTAG Header
TCK
TMS
Cyclone V GT
TDI
TDO
2.5 V
JTAG Slave
TCK
TMS
TDI
TDO
2.5 V
JTAG Slave
Analog
Switch
TCK
TMS
TDI
TDO
JTAG Slave
Analog
Switch
TCK
TMS
TDI
TDO
JTAG Slave
Chapter 2: Board Components
FPGA Configuration
Always
Enabled
FPGA
(in JTAG chain)
HSMC
HSMC
Port A
HSMC
HSMC
Port B
MAX V
Always
System
Enabled
Controller
(in JTAG chain)
August 2017 Altera Corporation