Altera Cyclone V Reference Manual page 54

2–46
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board Reference
T2
L3
L8
DDR3 x16 (U8)
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
K3
K9
J7
K7
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
D7
Cyclone V GT FPGA Development Board
Reference Manual
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Schematic Cyclone V GT
Signal Name Pin Number
AG31
DDR3B_RESETN
AM34
DDR3B_WEN
DDR3B_ZQ2
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
AE34
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
AF32
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
M33
DDR3B_DM4
DDR3B_DM5
DDR3B_DQ32
DDR3B_DQ33
DDR3B_DQ34
DDR3B_DQ35
DDR3B_DQ36
DDR3B_DQ37
DDR3B_DQ38
M34
DDR3B_DQ39
DDR3B_DQ40
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
H29 1.5-V SSTL Class I
K28 1.5-V SSTL Class I
K34 1.5-V SSTL Class I
L32 1.5-V SSTL Class I
R32 1.5-V SSTL Class I
R33 1.5-V SSTL Class I
N32 1.5-V SSTL Class I
G33 1.5-V SSTL Class I
1.5-V SSTL Class I
L27 1.5-V SSTL Class I
V33 1.5-V SSTL Class I
U33 1.5-V SSTL Class I
T31 1.5-V SSTL Class I
T30 1.5-V SSTL Class I
J31 1.5-V SSTL Class I
N29 1.5-V SSTL Class I
P27 1.5-V SSTL Class I
N27 1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
R30
Class I
Differential 1.5-V SSTL
R29
Class I
V27 1.5-V SSTL Class I
1.5-V SSTL Class I
K32 1.5-V SSTL Class I
T32 1.5-V SSTL Class I
N33 1.5-V SSTL Class I
T33 1.5-V SSTL Class I
L33 1.5-V SSTL Class I
T28 1.5-V SSTL Class I
J34 1.5-V SSTL Class I
T27 1.5-V SSTL Class I
1.5-V SSTL Class I
K33 1.5-V SSTL Class I
Chapter 2: Board Components
Memory
Description
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 5
August 2017 Altera Corporation