Altera Cyclone V Reference Manual page 28

Gt fpga development board

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2–20

Figure 2–5. Cyclone V GT FPGA Development Board Clocks

50 MHz

Reference

Clock Input

SMA

Si570

100 MHz

Default

Si571

148.5 MHz

Default

SDI

(148.5 M, 148.35 M)

Table 2–11. On-Board Oscillators (Part 1 of 2)

Source

CLKIN_50

CLKIN_MAX_50

CLK_125M_P

CLK_125M_N

Cyclone V GT FPGA Development Board

Reference Manual

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Figure 2–5

shows the default frequencies of all external clocks going to the

Cyclone V GT FPGA on the development board.

U52

50 MHz

Buffer

CLKIN_MAX_50

50 MHz

Output

SMA

PCIE_REFCLK_P/N

Buffer

100 MHz

Default

Table 2–11

lists the oscillators, its I/O standard, and voltages required for the

development board.

Schematic Signal

Frequency

Name

50.000 MHz

125.000 MHz

U13

REFCLK_QL1_P/N

(PCIe)

QL0

REFCLK_QL2_P/N

QL1

(SDI, HSMA)

REFCLK_QL3_P/N

QL2

(HSMB)

Cyclone V GT

I/O Standard

1.5-V CMOS

LVDS

Chapter 2: Board Components

CLK10

CLKINTOP_P/N

CLK5

CLK_125M_P/N

CLK6

CLKINA_50

CLK7

CLKIN_R_P/N

CLK2

CLKINBOT_P/N

Application

Pin Number

FPGA bank 5B (CLK6p) for

V28

general purpose logic

FPGA bank 5B (CLK6p) for

—

general purpose logic in the

MAX V CPLD

U31

FPGA bank 6A (CLK5p)

U30

FPGA bank 6A (CLK5n)

August 2017 Altera Corporation

Clock Circuitry

125 M

50 MHz

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Altera Cyclone V Reference Manual page 28

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